mainboard/intel/galileo: Add I2C chip initialization
Add I2C chip initialization for the Galileo boards. TEST=Build and run on Galileo Gen2 Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14829 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
Leroy P Leahy
parent
ac690b1e9b
commit
15843bdad0
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@ -16,3 +16,6 @@
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += reg_access.c
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@ -13,6 +13,9 @@
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* GNU General Public License for more details.
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*/
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/* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
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#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
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static const struct reg_script gen1_gpio_init[] = {
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/* Initialize the legacy GPIO controller */
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
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@ -49,5 +52,48 @@ static const struct reg_script gen1_gpio_init[] = {
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/* Toggle the Cypress reset line */
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REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
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REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
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REG_SCRIPT_END
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};
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static const struct reg_script gen1_i2c_0x20_init[] = {
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/* Route I2C pins to Arduino header:
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* Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
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*
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* I2C_SDA -> ANALOG_A4
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* I2C_SCL -> ANALOG_A5
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 1),
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REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
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/* Set all GPIO expander pins connected to the Reset Button as inputs
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* Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
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* (GPORT5_BIT1) as inputs
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
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REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
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REG_SCRIPT_END
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};
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static const struct reg_script gen1_i2c_0x21_init[] = {
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/* Route I2C pins to Arduino header:
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* Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
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*
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* I2C_SDA -> ANALOG_A4
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* I2C_SCL -> ANALOG_A5
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 1),
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REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
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REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
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/* Set all GPIO expander pins connected to the Reset Button as inputs
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* Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
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* (GPORT5_BIT1) as inputs
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
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REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
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REG_SCRIPT_END
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};
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@ -48,3 +48,28 @@ static const struct reg_script gen2_gpio_init[] = {
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REG_SCRIPT_END
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};
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static const struct reg_script gen2_i2c_init[] = {
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/* Route I2C to Arduino Shield connector:
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* Set AMUX1_IN (EXP2.P1_4) low
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* Configure AMUX1_IN (EXP2.P1_4) as an output
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*
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* I2C_SDA -> ANALOG_A4
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* I2C_SCL -> ANALOG_A5
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*/
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REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
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/* Set all GPIO expander pins connected to the Reset Button as inputs
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* Configure Reset Button(EXP1.P1_7) as an input
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* Disable pullup on Reset Button(EXP1.P1_7)
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* Configure Reset Button(EXP2.P1_7) as an input
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* Disable pullup on Reset Button(EXP2.P1_7)
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*/
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REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
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REG_I2C_OR(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, BIT7),
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REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
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REG_SCRIPT_END
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};
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@ -16,10 +16,29 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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#include "reg_access.h"
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#include "gen1.h"
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#include "gen2.h"
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void mainboard_gpio_i2c_init(device_t dev)
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{
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const struct reg_script *script;
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printk(BIOS_INFO, "Galileo I2C chip initialization\n");
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/* Determine the correct script for the board */
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if (IS_ENABLED(CONFIG_GALILEO_GEN2))
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script = gen2_i2c_init;
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else
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/* Determine which I2C address is in use */
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script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
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& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
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? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
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/* Initialize the I2C chips */
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reg_script_run(script);
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}
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void mainboard_gpio_init(void)
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{
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const struct reg_script *script;
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@ -0,0 +1,93 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/i2c.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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#include "reg_access.h"
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#if ENV_RAMSTAGE
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static uint64_t reg_read(struct reg_script_context *ctx)
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{
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int ret_code;
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const struct reg_script *step;
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uint8_t value = 0;
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step = ctx->step;
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switch (step->id) {
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default:
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printk(BIOS_ERR,
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"ERROR - Unknown register set (0x%08x)!\n",
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step->id);
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ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
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break;
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case GEN1_I2C_GPIO_EXP_0x20:
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case GEN1_I2C_GPIO_EXP_0x21:
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case GEN2_I2C_GPIO_EXP0:
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case GEN2_I2C_GPIO_EXP1:
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case GEN2_I2C_GPIO_EXP2:
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case GEN2_I2C_LED_PWM:
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if (ctx->display_features)
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printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id);
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ret_code = i2c_readb(0, step->id, (UINT8)step->reg, &value);
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ASSERT(ret_code == 2);
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break;
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}
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return value;
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}
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static void reg_write(struct reg_script_context *ctx)
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{
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int ret_code;
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const struct reg_script *step;
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uint8_t value;
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step = ctx->step;
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switch (step->id) {
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default:
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printk(BIOS_ERR,
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"ERROR - Unknown register set (0x%08x)!\n",
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step->id);
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ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
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break;
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case GEN1_I2C_GPIO_EXP_0x20:
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case GEN1_I2C_GPIO_EXP_0x21:
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case GEN2_I2C_GPIO_EXP0:
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case GEN2_I2C_GPIO_EXP1:
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case GEN2_I2C_GPIO_EXP2:
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case GEN2_I2C_LED_PWM:
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case RMU_TEMP_REGS:
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if (ctx->display_features)
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printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id);
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value = (UINT8)step->value;
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ret_code = i2c_writeb(0, step->id, (UINT8)step->reg, value);
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ASSERT(ret_code == 2);
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break;
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}
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}
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const struct reg_script_bus_entry mainboard_reg_script_bus_table = {
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MAINBOARD_TYPE, reg_read, reg_write
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};
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REG_SCRIPT_BUS_ENTRY(mainboard_reg_script_bus_table);
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#endif /* ENV_RAMSTAGE */
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@ -0,0 +1,97 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _GALILEO_REG_ACCESS_H_
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#define _GALILEO_REG_ACCESS_H_
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#include <fsp/util.h>
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#include <reg_script.h>
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#include <soc/IntelQNCConfig.h>
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#include <soc/QuarkNcSocId.h>
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#include <soc/reg_access.h>
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enum {
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MAINBOARD_TYPE = REG_SCRIPT_TYPE_MAINBOARD_BASE,
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/* Add additional mainboard access types here*/
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};
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enum {
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GEN1_I2C_GPIO_EXP_0x20 = 0x20, /* Cypress CY8C9540A */
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GEN1_I2C_GPIO_EXP_0x21 = 0x21, /* Cypress CY8C9540A */
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GEN2_I2C_GPIO_EXP0 = 0x25, /* NXP PCAL9535A */
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GEN2_I2C_GPIO_EXP1 = 0x26, /* NXP PCAL9535A */
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GEN2_I2C_GPIO_EXP2 = 0x27, /* NXP PCAL9535A */
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GEN2_I2C_LED_PWM = 0x47, /* NXP PCAL9685 */
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};
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/* Cypress CY8C9548A registers */
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#define GEN1_GPIO_EXP_INPUT0 0x00
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#define GEN1_GPIO_EXP_INPUT1 0x01
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#define GEN1_GPIO_EXP_INPUT2 0x02
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#define GEN1_GPIO_EXP_INPUT3 0x03
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#define GEN1_GPIO_EXP_INPUT4 0x04
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#define GEN1_GPIO_EXP_INPUT5 0x05
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#define GEN1_GPIO_EXP_OUTPUT0 0x08
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#define GEN1_GPIO_EXP_OUTPUT1 0x09
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#define GEN1_GPIO_EXP_OUTPUT2 0x0a
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#define GEN1_GPIO_EXP_OUTPUT3 0x0b
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#define GEN1_GPIO_EXP_OUTPUT4 0x0c
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#define GEN1_GPIO_EXP_OUTPUT5 0x0d
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#define GEN1_GPIO_EXP_PORT_SELECT 0x18
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#define GEN1_GPIO_EXP_PORT_DIR 0x1c
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/* NXP PCAL9535A registers */
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#define GEN2_GPIO_EXP_INPUT0 0x00
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#define GEN2_GPIO_EXP_INPUT1 0x01
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#define GEN2_GPIO_EXP_OUTPUT0 0x02
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#define GEN2_GPIO_EXP_OUTPUT1 0x03
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#define GEN2_GPIO_EXP_POLARITY0 0x04
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#define GEN2_GPIO_EXP_POLARITY1 0x05
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#define GEN2_GPIO_EXP_CONFIG0 0x06
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#define GEN2_GPIO_EXP_CONFIG1 0x07
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#define GEN2_GPIO_EXP_INPUT_LATCH0 0x44
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#define GEN2_GPIO_EXP_INPUT_LATCH1 0x45
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#define GEN2_GPIO_EXP_PULL_UP_DOWN_EN0 0x46
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#define GEN2_GPIO_EXP_PULL_UP_DOWN_EN1 0x47
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#define GEN2_GPIO_EXP_PULL_UP_DOWN_SEL0 0x46
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#define GEN2_GPIO_EXP_PULL_UP_DOWN_SEL1 0x47
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#define MAINBOARD_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \
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_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, MAINBOARD_TYPE, \
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size_, reg_, mask_, value_, timeout_, reg_set_)
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/* I2C chip register access macros */
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#define REG_I2C_ACCESS(cmd_, reg_, mask_, value_, timeout_, slave_addr_) \
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MAINBOARD_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_8, mask_, value_, \
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timeout_, slave_addr_)
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#define REG_I2C_READ(slave_addr_, reg_) \
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REG_I2C_ACCESS(READ, reg_, 0, 0, 0, slave_addr_)
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#define REG_I2C_WRITE(slave_addr_, reg_, value_) \
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REG_I2C_ACCESS(WRITE, reg_, 0, value_, 0, slave_addr_)
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#define REG_I2C_AND(slave_addr_, reg_, value_) \
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REG_I2C_RMW(slave_addr_, reg_, value_, 0)
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#define REG_I2C_RMW(slave_addr_, reg_, mask_, value_) \
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REG_I2C_ACCESS(RMW, reg_, mask_, value_, 0, slave_addr_)
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#define REG_I2C_RXW(slave_addr_, reg_, mask_, value_) \
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REG_I2C_ACCESS(RXW, reg_, mask_, value_, 0, slave_addr_)
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#define REG_I2C_OR(slave_addr_, reg_, value_) \
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REG_I2C_RMW(slave_addr_, reg_, 0xff, value_)
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#define REG_I2C_POLL(slave_addr_, reg_, mask_, value_, timeout_) \
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REG_I2C_ACCESS(POLL, reg_, mask_, value_, timeout_, slave_addr_)
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#define REG_I2C_XOR(slave_addr_, reg_, value_) \
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REG_I2C_RXW(slave_addr_, reg_, 0xff, value_)
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#endif /* _GALILEO_REG_ACCESS_H_ */
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