drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E

Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.

BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.

Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>

src/drivers/genesyslogic/gl9763e/Kconfig

@@ -1,2 +1,8 @@
 config DRIVERS_GENESYSLOGIC_GL9763E
-	bool
+	bool "Genesys Logic GL9763E"
+	default n
+
+config DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX
+	bool "Set L1 entry delay to MAX"
+	depends on DRIVERS_GENESYSLOGIC_GL9763E
+	default n

src/drivers/genesyslogic/gl9763e/gl9763e.c

@@ -23,6 +23,11 @@ static void gl9763e_init(struct device *dev)
 	pci_or_config32(dev, SCR, SCR_AXI_REQ);
 	/* Disable L0s support */
 	pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S);
+
+	if (CONFIG(DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX))
+		/* Set  L1 entry delay to MAX */
+		pci_or_config32(dev, CFG_REG_2, CFG_REG_2_L1DLY_MAX);
+
 	/* Set SSC to 30000 ppm */
 	pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM);
 	/* Enable SSC */

src/drivers/genesyslogic/gl9763e/gl9763e.h

@@ -14,6 +14,7 @@
 
 #define CFG_REG_2	0x8A4
 #define   CFG_REG_2_L0S	BIT(11)
+#define   CFG_REG_2_L1DLY_MAX	(0x3FF << 19)
 
 #define PLL_CTL		0x938
 #define   PLL_CTL_SSC	BIT(19)