diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 5c5e56b071..492508ef40 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -122,7 +122,7 @@ enum timestamp_id {
 	TS_START_CSE_FW_SYNC = 948,
 	TS_END_CSE_FW_SYNC = 949,
 
-	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+	/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
 	TS_FSP_MEMORY_INIT_START = 950,
 	TS_FSP_MEMORY_INIT_END = 951,
 	TS_FSP_TEMP_RAM_EXIT_START = 952,
@@ -140,6 +140,9 @@ enum timestamp_id {
 	TS_FSP_MEMORY_INIT_LOAD = 970,
 	TS_FSP_SILICON_INIT_LOAD = 971,
 
+	/* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */
+	TS_ME_ROM_START = 990,
+
 	/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
 
 	/* Depthcharge entry IDs start at 1000 */
@@ -283,6 +286,7 @@ static const struct timestamp_id_to_name {
 	{ TS_ME_RECEIVED_CRDA_FROM_PMC,	"CSE received 'CPU Reset Done Ack sent' from PMC"},
 	{ TS_START_CSE_FW_SYNC,		"starting CSE firmware sync"},
 	{ TS_END_CSE_FW_SYNC,		"finished CSE firmware sync"},
+	{ TS_ME_ROM_START,		"CSME ROM started execution"},
 
 	/* FSP related timestamps */
 	{ TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },