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soc/amd/common/block/lpc/lpc: simplify index handling in read resources 

Now that we don't need to find a specific resource in the set resources
function any more, there's no need to use hard-coded indices for the
fixed resources. Instead use an index variable that gets incremented
after each fixed resource got added. The index now starts at 0 instead
of at 1, but now the only requirement is that those indices are unique.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74849
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-04-29 02:56:07 +02:00
parent b70b980dda
commit 1591f8437c
1 changed files with 6 additions and 5 deletions
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11
src/soc/amd/common/block/lpc/lpc.c
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@ -106,6 +106,7 @@ static void lpc_init(struct device *dev)
static void lpc_read_resources(struct device *dev) static void lpc_read_resources(struct device *dev)
{ {
struct resource *res; struct resource *res;
unsigned long idx = 0;
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
@ -118,20 +119,20 @@ static void lpc_read_resources(struct device *dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED; IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */
mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE, mmio_range(dev, idx++, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE); FLASH_BELOW_4GB_MAPPING_REGION_SIZE);
/* Add a memory resource for the SPI BAR. */ /* Add a memory resource for the SPI BAR. */
mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); mmio_range(dev, idx++, SPI_BASE_ADDRESS, 4 * KiB);
/* Add a memory resource for the eSPI MMIO */ /* Add a memory resource for the eSPI MMIO */
mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
/* FCH IOAPIC */ /* FCH IOAPIC */
mmio_range(dev, 4, IO_APIC_ADDR, 4 * KiB); mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);
/* HPET */ /* HPET */
mmio_range(dev, 5, HPET_BASE_ADDRESS, 4 * KiB); mmio_range(dev, idx++, HPET_BASE_ADDRESS, 4 * KiB);
compact_resources(dev); compact_resources(dev);
} }