drivers/intel/fsp2_0: Add preload_fspm and preload_fsps

In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.

BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/drivers/intel/fsp2_0/include/fsp/api.h

@@ -32,7 +32,9 @@ enum fsp_notify_phase {
 };
 
 /* Main FSP stages */
+void preload_fspm(void);
 void fsp_memory_init(bool s3wake);
+void preload_fsps(void);
 void fsp_silicon_init(void);
 
 /*

src/drivers/intel/fsp2_0/memory_init.c

@@ -340,6 +340,15 @@ static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unus
 	return (void *)fspm_begin;
 }
 
+void preload_fspm(void)
+{
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS);
+	cbfs_preload(CONFIG_FSP_M_CBFS);
+}
+
 void fsp_memory_init(bool s3wake)
 {
 	struct range_entry prog_ranges[2];

src/drivers/intel/fsp2_0/silicon_init.c

@@ -230,6 +230,15 @@ void fsps_load(void)
 	load_done = 1;
 }
 
+void preload_fsps(void)
+{
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS);
+	cbfs_preload(CONFIG_FSP_S_CBFS);
+}
+
 void fsp_silicon_init(void)
 {
 	timestamp_add_now(TS_FSP_SILICON_INIT_LOAD);