From 15aa0a56ce751f7c36402fe74b6bc3c636c26307 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <jacz@semihalf.com>
Date: Thu, 1 Jun 2023 12:11:50 +0000
Subject: [PATCH] mb/google/rex/variants/ovis: Add SSD card config

BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis

Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jan Dabros <dabros@google.com>
---
 src/mainboard/google/rex/variants/ovis/overridetree.cb | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb
index 2d43a0e122..bc10cd1a97 100644
--- a/src/mainboard/google/rex/variants/ovis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb
@@ -28,6 +28,14 @@ chip soc/intel/meteorlake
 	}"
 
 	device domain 0 on
+		device ref pcie_rp11 on
+			# Enable SSD Card PCIE 11 using clk 7
+			register "pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 7,
+				.clk_req = 7,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end	# PCIE11 SSD card
 		device ref i2c4 on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""