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Intel HD Audio: clean up initialization code 

- Some initialization steps were done twice
- One step was missing for Panther Point HDA
- Added a 1ms delay after reset
- Increased timeout to 1ms for all codec operations

Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer 2012-11-14 12:25:15 -08:00 committed by Ronald G. Minnich
parent 6dcceddff5
commit 15ba2bcf2d
1 changed files with 20 additions and 23 deletions
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43
src/southbridge/intel/bd82x6x/azalia.c
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@ -120,10 +120,9 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
static int wait_for_ready(u32 base) static int wait_for_ready(u32 base)
{ {
/* Use a 50 usec timeout - the Linux kernel uses the /* Use a 1msec timeout */
* same duration */
int timeout = 50; int timeout = 1000;
while(timeout--) { while(timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG); u32 reg32 = read32(base + HDA_ICII_REG);
@ -150,10 +149,9 @@ static int wait_for_valid(u32 base)
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
write32(base + HDA_ICII_REG, reg32); write32(base + HDA_ICII_REG, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the /* Use a 1msec timeout */
* same duration */
int timeout = 50; int timeout = 1000;
while(timeout--) { while(timeout--) {
reg32 = read32(base + HDA_ICII_REG); reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
@ -254,12 +252,12 @@ static void azalia_init(struct device *dev)
if (RCBA32(0x2030) & (1 << 31)) { if (RCBA32(0x2030) & (1 << 31)) {
reg32 = pci_mmio_read_config32(dev, 0x120); reg32 = pci_mmio_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01; reg32 &= 0xf8ffff01;
reg32 |= (1 << 24); // 25 for server reg32 |= (1 << 24); // 2 << 24 for server
reg32 |= RCBA32(0x2030) & 0xfe; reg32 |= RCBA32(0x2030) & 0xfe;
pci_mmio_write_config32(dev, 0x120, reg32); pci_mmio_write_config32(dev, 0x120, reg32);
reg16 = pci_mmio_read_config16(dev, 0x78); reg16 = pci_mmio_read_config16(dev, 0x78);
reg16 &= ~(1 << 11); reg16 |= (1 << 11);
pci_mmio_write_config16(dev, 0x78, reg16); pci_mmio_write_config16(dev, 0x78, reg16);
} else } else
printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
@ -269,12 +267,9 @@ static void azalia_init(struct device *dev)
pci_mmio_write_config32(dev, 0x114, reg32); pci_mmio_write_config32(dev, 0x114, reg32);
// Set VCi enable bit // Set VCi enable bit
if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | reg32 = pci_mmio_read_config32(dev, 0x120);
(1 << 25) | (1 << 26))) { reg32 |= (1 << 31);
reg32 = pci_mmio_read_config32(dev, 0x120); pci_mmio_write_config32(dev, 0x120, reg32);
reg32 |= (1 << 31);
pci_mmio_write_config32(dev, 0x120, reg32);
}
// Enable HDMI codec: // Enable HDMI codec:
reg32 = pci_read_config32(dev, 0xc4); reg32 = pci_read_config32(dev, 0xc4);
@ -285,15 +280,6 @@ static void azalia_init(struct device *dev)
reg8 |= (1 << 6); reg8 |= (1 << 6);
pci_write_config8(dev, 0x43, reg8); pci_write_config8(dev, 0x43, reg8);
/* Additional programming steps */
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 13) | (1 << 10);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xd0);
reg32 &= ~(1 << 31);
pci_write_config32(dev, 0xd0, reg32);
/* Additional programming steps */ /* Additional programming steps */
reg32 = pci_read_config32(dev, 0xc4); reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 13); reg32 |= (1 << 13);
@ -307,6 +293,13 @@ static void azalia_init(struct device *dev)
reg32 &= ~(1 << 31); reg32 &= ~(1 << 31);
pci_write_config32(dev, 0xd0, reg32); pci_write_config32(dev, 0xd0, reg32);
if (dev->device == 0x1e20) {
/* Additional step on Panther Point */
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 17);
pci_write_config32(dev, 0xc4, reg32);
}
/* Set Bus Master */ /* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
@ -314,9 +307,13 @@ static void azalia_init(struct device *dev)
pci_write_config8(dev, 0x3c, 0x0a); // unused? pci_write_config8(dev, 0x3c, 0x0a); // unused?
/* Codec Initialization Programming Sequence */ /* Codec Initialization Programming Sequence */
/* Take controller out of reset */
reg32 = read32(base + 0x08); reg32 = read32(base + 0x08);
reg32 |= (1 << 0); reg32 |= (1 << 0);
write32(base + 0x08, reg32); write32(base + 0x08, reg32);
/* Wait 1ms */
udelay(1000);
// //
reg8 = pci_read_config8(dev, 0x40); // Audio Control reg8 = pci_read_config8(dev, 0x40); // Audio Control