Following patch adds resume (exit from self refresh) support for AMD K8 revF
CPUs. It handles both type of erratas on those CPUs. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
parent
33cafe5bfb
commit
15bf50d820
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@ -73,7 +73,11 @@ static void enable_fid_change(void)
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// dword = 0x00070000; /* enable FID/VID change */
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pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
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#if HAVE_ACPI_RESUME
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dword = 0x21132113;
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#else
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dword = 0x00132113;
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#endif
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pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x84, dword);
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}
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@ -0,0 +1,189 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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void exit_from_self(int controllers, const struct mem_controller *ctrl,
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struct sys_info *sysinfo)
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{
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int i;
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u32 dcl, dch;
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u32 pcidev;
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u8 bitmask;
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u8 is_post_rev_g;
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u32 cpuid;
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for (i = 0; i < controllers; i++) {
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if (!sysinfo->ctrl_present[i])
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continue;
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/* Skip everything if I don't have any memory on this controller */
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dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
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if (!(dch & DCH_MemClkFreqVal)) {
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continue;
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}
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cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
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is_post_rev_g = ((cpuid & 0xfff00) > 0x50f00);
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/* ChipKill */
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dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
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if (dcl & DCL_DimmEccEn) {
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u32 mnc;
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printk_spew("ECC enabled\n");
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mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
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mnc |= MNC_ECC_EN;
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if (dcl & DCL_Width128) {
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mnc |= MNC_CHIPKILL_EN;
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}
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pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
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}
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printk_debug("before resume errata #%d\n",
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(is_post_rev_g) ? 270 : 125);
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/*
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1. Restore memory controller registers as normal.
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2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only)
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3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register).
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4. Wait at least 750 us.
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5. Clear the EnDramInit bit.
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6. Clear the DisAutoRefresh bit. (270 only)
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7. Read the value of Dev:2x80 and write that value back to Dev:2x80.
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8. Set the exit from the self refresh bit (Dev:2x90[1]).
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9. Clear the exit from self refresh bit immediately.
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Note: Steps 8 and 9 must be executed in a single 64-byte aligned uninterrupted instruction stream.
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*/
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enable_lapic();
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init_timer();
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printk_debug("before exit errata - timer enabled\n");
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if (is_post_rev_g) {
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dcl =
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pci_read_config32(ctrl[i].f2,
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DRAM_TIMING_HIGH);
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dcl |= (1 << 18);
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pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
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dcl);
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}
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dcl = DI_EnDramInit;
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pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
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udelay(800);
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printk_debug("before exit errata - after mdelay\n");
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dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
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dcl &= ~DI_EnDramInit;
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pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
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if (is_post_rev_g) {
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dcl =
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pci_read_config32(ctrl[i].f2,
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DRAM_TIMING_HIGH);
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dcl &= ~(1 << 18);
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pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
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dcl);
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}
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dcl = pci_read_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP);
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pci_write_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP, dcl);
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/* I was unable to do that like: ctrl[i].f2->path.pci.devfn << 8 */
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pcidev =
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0x80000000 | ((((ctrl[i].node_id + 0x18) << 3) | 0x2)
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<< 8) | 0x90;
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printk_debug("pcidev is %x\n", pcidev);
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bitmask = 2;
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__asm__ __volatile__("pushl %0\n\t"
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"movw $0xcf8, %%dx\n\t"
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"out %%eax, (%%dx)\n\t"
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"movw $0xcfc, %%dx\n\t"
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"inl %%dx, %%eax\n\t"
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"orb %1, %%al\n\t"
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"not %1\n\t"
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".align 64\n\t"
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"outl %%eax, (%%dx) \n\t"
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"andb %1, %%al\n\t"
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"outl %%eax, (%%dx)\n\t"
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"popl %0\n\t"::"a"(pcidev),
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"q"(bitmask):"edx");
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}
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printk_debug("after exit errata\n");
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for (i = 0; i < controllers; i++) {
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u32 dcm;
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if (!sysinfo->ctrl_present[i])
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continue;
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/* Skip everything if I don't have any memory on this controller */
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if (sysinfo->meminfo[i].dimm_mask == 0x00)
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continue;
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printk_debug("Exiting memory from self refresh: ");
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int loops = 0;
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do {
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loops++;
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if ((loops & 1023) == 0) {
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printk_debug(".");
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}
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dcm =
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pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
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} while (((dcm & DCM_MemClrStatus) ==
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0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
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if (loops >= TIMEOUT_LOOPS) {
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printk_debug("timeout with with cntrl[%d]\n", i);
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continue;
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}
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printk_debug(" done\n");
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}
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#if HW_MEM_HOLE_SIZEK != 0
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/* init hw mem hole here */
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/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
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set_hw_mem_hole(controllers, ctrl);
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#endif
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/* store tom to sysinfo, and it will be used by dqs_timing */
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{
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msr_t msr;
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//[1M, TOM)
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msr = rdmsr(TOP_MEM);
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sysinfo->tom_k = ((msr.hi << 24) | (msr.lo >> 8)) >> 2;
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//[4G, TOM2)
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msr = rdmsr(TOP_MEM2);
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sysinfo->tom2_k = ((msr.hi << 24) | (msr.lo >> 8)) >> 2;
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}
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for (i = 0; i < controllers; i++) {
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if (!sysinfo->ctrl_present[i])
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continue;
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/* Skip everything if I don't have any memory on this controller */
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if (sysinfo->meminfo[i].dimm_mask == 0x00)
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continue;
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dqs_restore_MC_NVRAM((ctrl + i)->f2);
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sysinfo->mem_trained[i] = 1; // mem was trained
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}
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}
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@ -3009,11 +3009,17 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
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}
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#endif
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#include "exit_from_self.c"
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static void sdram_enable(int controllers, const struct mem_controller *ctrl,
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struct sys_info *sysinfo)
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{
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int i;
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#ifdef ACPI_IS_WAKEUP_EARLY
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int suspend = acpi_is_wakeup_early();
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#else
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int suspend = 0;
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#endif
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#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
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unsigned cpu_f0_f1[8];
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@ -3060,6 +3066,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
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printk_debug("\n");
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#endif
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/* lets override the rest of the routine */
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if (suspend) {
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printk_debug("Wakeup!\n");
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exit_from_self(controllers, ctrl, sysinfo);
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printk_debug("Mem running !\n");
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return;
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}
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for (i = 0; i < controllers; i++) {
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uint32_t dcl, dch;
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if (!sysinfo->ctrl_present[ i ])
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@ -1821,10 +1821,94 @@ static void set_sysinfo_in_ram(unsigned val)
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set_htic_bit(0, val, 9);
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}
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#ifdef S3_NVRAM_EARLY
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
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#else
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
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}
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
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die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");
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}
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#endif
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static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos) {
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u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
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return s3_save_nvram_early(dword, size, nvram_pos);
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}
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static int load_index_to_pos(unsigned int dev, int size, int index, int nvram_pos) {
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u32 old_dword = pci_read_config32_index_wait(dev, 0x98, index);
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nvram_pos = s3_load_nvram_early(size, &old_dword, nvram_pos);
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pci_write_config32_index_wait(dev, 0x98, index, old_dword);
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return nvram_pos;
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}
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static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos) {
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/* 30 bytes per channel */
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ch *= 0x20;
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pos = load_index_to_pos(dev, 4, 0x00 + ch, pos);
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pos = load_index_to_pos(dev, 4, 0x01 + ch, pos);
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pos = load_index_to_pos(dev, 4, 0x02 + ch, pos);
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pos = load_index_to_pos(dev, 1, 0x03 + ch, pos);
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pos = load_index_to_pos(dev, 4, 0x04 + ch, pos);
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pos = load_index_to_pos(dev, 4, 0x05 + ch, pos);
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pos = load_index_to_pos(dev, 4, 0x06 + ch, pos);
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pos = load_index_to_pos(dev, 1, 0x07 + ch, pos);
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pos = load_index_to_pos(dev, 1, 0x10 + ch, pos);
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pos = load_index_to_pos(dev, 1, 0x13 + ch, pos);
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pos = load_index_to_pos(dev, 1, 0x16 + ch, pos);
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pos = load_index_to_pos(dev, 1, 0x19 + ch, pos);
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return pos;
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}
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static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos) {
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/* 30 bytes per channel */
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ch *= 0x20;
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pos = save_index_to_pos(dev, 4, 0x00 + ch, pos);
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pos = save_index_to_pos(dev, 4, 0x01 + ch, pos);
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pos = save_index_to_pos(dev, 4, 0x02 + ch, pos);
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pos = save_index_to_pos(dev, 1, 0x03 + ch, pos);
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pos = save_index_to_pos(dev, 4, 0x04 + ch, pos);
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pos = save_index_to_pos(dev, 4, 0x05 + ch, pos);
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pos = save_index_to_pos(dev, 4, 0x06 + ch, pos);
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pos = save_index_to_pos(dev, 1, 0x07 + ch, pos);
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pos = save_index_to_pos(dev, 1, 0x10 + ch, pos);
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pos = save_index_to_pos(dev, 1, 0x13 + ch, pos);
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pos = save_index_to_pos(dev, 1, 0x16 + ch, pos);
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pos = save_index_to_pos(dev, 1, 0x19 + ch, pos);
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return pos;
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}
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static void dqs_save_MC_NVRAM(unsigned int dev) {
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int pos = 0;
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u32 reg;
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printk_debug("DQS SAVE NVRAM: %x\n", dev);
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pos = dqs_save_MC_NVRAM_ch(dev, 0, pos);
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pos = dqs_save_MC_NVRAM_ch(dev, 1, pos);
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/* save the maxasync lat here */
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reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
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pos = s3_save_nvram_early(reg, 4, pos);
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}
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static void dqs_restore_MC_NVRAM(unsigned int dev) {
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int pos = 0;
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u32 reg;
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printk_debug("DQS RESTORE FROM NVRAM: %x\n", dev);
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pos = dqs_load_MC_NVRAM_ch(dev, 0, pos);
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pos = dqs_load_MC_NVRAM_ch(dev, 1, pos);
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/* load the maxasync lat here */
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pos = s3_load_nvram_early(4, ®, pos);
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reg &= (DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
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reg |= pci_read_config32(dev, DRAM_CONFIG_HIGH);
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pci_write_config32(dev, DRAM_CONFIG_HIGH, reg);
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}
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#if MEM_TRAIN_SEQ == 0
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#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
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static void dqs_timing(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo)
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#else
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@ -1891,6 +1975,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
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if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
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printk_debug(" done\r\n");
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sysinfo->mem_trained[i]=1;
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dqs_save_MC_NVRAM((ctrl+i)->f2);
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}
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out:
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