soc/intel/common/block/cse: Clear post code before reset

To avoid "unknown post code 0x55" entries in the event log on cold boot
clear the post code before doing the CSE initiated reset.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/common/block/cse/cse.c

@@ -555,6 +555,9 @@ int heci_reset(void)
 {
 	uint32_t csr;
 
+	/* Clear post code to prevent eventlog entry from unknown code. */
+	post_code(0);
+
 	/* Send reset request */
 	csr = read_host_csr();
 	csr |= (CSR_RESET | CSR_IG);