{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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9514d47d3c
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15ccbf042d
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@ -65,20 +65,8 @@ static const char *pcie_acpi_name(const struct device *dev)
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}
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}
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#endif
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#endif
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static void
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pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device)
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{
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/* NOTE: This is not the default position! */
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if (!ven || !device)
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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else
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (ven & 0xffff));
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -649,16 +649,6 @@ static void pch_pcie_enable(struct device *dev)
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root_port_commit_config();
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root_port_commit_config();
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}
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}
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static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
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unsigned int device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device)
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pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
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else
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pci_write_config32(dev, 0x94, (device << 16) | vendor);
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}
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static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
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static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
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{
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{
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/* Set max snoop and non-snoop latency for Broadwell */
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/* Set max snoop and non-snoop latency for Broadwell */
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@ -666,7 +656,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
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}
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}
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static struct pci_operations pcie_ops = {
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static struct pci_operations pcie_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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};
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};
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@ -25,8 +25,6 @@
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
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#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
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/* PCI-E Sub-System ID */
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#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
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static void pch_pcie_init(struct device *dev)
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static void pch_pcie_init(struct device *dev)
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{
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{
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@ -72,16 +70,9 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
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PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
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PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
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}
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}
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static void pcie_dev_set_subsystem(struct device *dev,
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unsigned int vendor, unsigned int device)
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{
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pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations pcie_ops = {
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static struct pci_operations pcie_ops = {
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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.set_subsystem = pcie_dev_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -306,21 +306,8 @@ static const char *pch_pcie_acpi_name(const struct device *dev)
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return NULL;
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return NULL;
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}
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}
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static void pcie_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -252,22 +252,8 @@ static void ich_pcie_enable(struct device *dev)
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root_port_commit_config(dev);
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root_port_commit_config(dev);
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}
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}
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static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
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unsigned int device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -95,19 +95,6 @@ static void pci_init(struct device *dev)
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}
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}
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}
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}
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static void pcie_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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/* NOTE: 0x94 is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static void pch_pciexp_scan_bridge(struct device *dev)
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static void pch_pciexp_scan_bridge(struct device *dev)
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{
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{
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struct southbridge_intel_i82801ix_config *config = dev->chip_info;
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struct southbridge_intel_i82801ix_config *config = dev->chip_info;
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@ -121,7 +108,7 @@ static void pch_pciexp_scan_bridge(struct device *dev)
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}
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -95,19 +95,6 @@ static void pci_init(struct device *dev)
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}
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}
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}
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}
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static void pcie_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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/* NOTE: 0x94 is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static void pch_pciexp_scan_bridge(struct device *dev)
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static void pch_pciexp_scan_bridge(struct device *dev)
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{
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{
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struct southbridge_intel_i82801jx_config *config = dev->chip_info;
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struct southbridge_intel_i82801jx_config *config = dev->chip_info;
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@ -121,7 +108,7 @@ static void pch_pciexp_scan_bridge(struct device *dev)
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}
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -727,21 +727,8 @@ static void pch_pcie_enable(struct device *dev)
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root_port_commit_config();
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root_port_commit_config();
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}
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}
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static void pcie_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations pci_ops = {
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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};
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static struct device_operations device_ops = {
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static struct device_operations device_ops = {
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@ -200,8 +200,8 @@ static void rl5c476_set_subsystem(struct device *dev, unsigned vendor,
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/* Enable subsystem id register writes */
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/* Enable subsystem id register writes */
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pci_write_config16(dev, 0x82, miscreg | 0x40);
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pci_write_config16(dev, 0x82, miscreg | 0x40);
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pci_write_config16(dev, 0x40, vendor);
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pci_dev_set_subsystem(dev, vendor, device);
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pci_write_config16(dev, 0x42, device);
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/* restore original contents */
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/* restore original contents */
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pci_write_config16(dev, 0x82, miscreg);
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pci_write_config16(dev, 0x82, miscreg);
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}
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}
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@ -46,8 +46,7 @@ static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor,
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* to the sub-vendor/device ids at 40 and 42.
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* to the sub-vendor/device ids at 40 and 42.
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*/
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*/
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pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10);
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pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10);
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pci_write_config16(dev, 0x40, vendor);
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pci_dev_set_subsystem(dev, vendor, device);
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pci_write_config16(dev, 0x42, device);
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pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10);
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pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10);
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}
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}
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