GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

northbridge/amd/amdfam10: Update RAM speed table with DDR3 values 

Change-Id: I8ab7b2cd9bf36d53b744a11d32dd40c750149567
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12272
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-10-30 18:53:48 -05:00 committed by Ronald G. Minnich
parent 0746452a26
commit 160ad6aa75
1 changed files with 32 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -946,6 +946,7 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur
static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed)
{
if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
switch (speed) {
case 1:
return 200;
@ -960,6 +961,24 @@ static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed)
default:
return 0;
}
} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
switch (speed) {
case 3:
return 333;
case 4:
return 400;
case 5:
return 533;
case 6:
return 667;
case 7:
return 800;
default:
return 0;
}
} else {
return 0;
}
}
static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, unsigned long *current)