chromeos chipsets: select RTC usage

Since RTC is now a Kconfig ensure RTC is selected on the
x86 chipsets which are in Chrome OS devices. This allows
the eventlog to have proper timestamps instead of all
zeros.

BUG=chrome-os-partner:55993

Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/Kconfig

@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select POSTCAR_STAGE
 	select REG_SCRIPT
 	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
+	select RTC
 	select SMM_TSEG
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI

src/soc/intel/baytrail/Kconfig

@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select REG_SCRIPT
+	select RTC
 	select SMM_TSEG
 	select SMP
 	select SPI_FLASH

src/soc/intel/braswell/Kconfig

@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_COMMON_CLOCK
 	select PLATFORM_USES_FSP1_1
 	select REG_SCRIPT
+	select RTC
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_RESET

src/soc/intel/broadwell/Kconfig

@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_COMMON_CLOCK
 	select PCIEXP_CLK_PM
 	select PCIEXP_L1_SUB_STATE
+	select RTC
 	select SMM_TSEG
 	select SMP
 	select SPI_FLASH

src/soc/intel/skylake/Kconfig

@@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
 	select REG_SCRIPT
 	select RELOCATABLE_MODULES
 	select RELOCATABLE_RAMSTAGE
+	select RTC
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_LPSS_I2C

src/southbridge/intel/bd82x6x/Kconfig

@@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select ACPI_SATA_GENERATOR
 	select HAVE_INTEL_FIRMWARE
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
+	select RTC
 
 config EHCI_BAR
 	hex

src/southbridge/intel/lynxpoint/Kconfig

@@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SPI_FLASH
 	select HAVE_INTEL_FIRMWARE
 	select HAVE_SPI_CONSOLE_SUPPORT
+	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
 
 config INTEL_LYNXPOINT_LP