soc/intel/broadwell: Remove unnecessary array
The MAD_DIMM registers can be read within the loop just fine. Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -87,6 +87,9 @@
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#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x)))
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#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x)))
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/* Memory controller characteristics */
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#define NUM_CHANNELS 2
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#define MAD_CHNL 0x5000
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#define MAD_DIMM(ch) (0x5004 + 4 * (ch))
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@ -27,12 +27,9 @@
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*/
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static void report_memory_config(void)
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{
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u32 addr_decode_ch[2];
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int i;
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const u32 addr_decoder_common = MCHBAR32(MAD_CHNL);
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addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0));
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addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1));
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
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@ -42,8 +39,8 @@ static void report_memory_config(void)
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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for (i = 0; i < NUM_CHANNELS; i++) {
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const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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