mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7

Uldren does not have PCIE device and should disable PCIE RP7 and
GPP_D7 for preventing PCIe controller not power gate in S0ix.

BUG=b:283735051
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6'
[SPEW ]  PCI: 00:1c.6: enabled 0
[SPEW ]  PCI: 00:1c.6: enabled 0
2. GPP_D7: iotools mmio_read32 0xfd6d0ab0
0x44000300

Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>

src/mainboard/google/brya/variants/uldren/gpio.c

@@ -21,6 +21,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO(GPP_C1, 1, DEEP),
 	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D7  : SRCCLKREQ2# ==> NC */
+	PAD_NC(GPP_D7, NONE),
 	/* D8  : SRCCLKREQ3# ==> NC */
 	PAD_NC(GPP_D8, NONE),
 	/* D15 : ISH_UART0_RTS# ==> NC */

src/mainboard/google/brya/variants/uldren/overridetree.cb

@@ -353,6 +353,7 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref pcie_rp7 off end
 		device ref hda on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98360A""