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soc/intel/tigerlake: Disable VMD 

It's already disabled by FSP default but disable VMD by devicetree
to remove dependency with FSP default setting.

BUG=None
Branch=None
Test=Build TGLRVP and boot up and check FSP log for checking VMD is
disabled.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-05-05 09:10:13 -07:00 committed by Patrick Georgi
parent f381d97856
commit 165efa1b86
4 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -164,7 +164,7 @@ chip soc/intel/tigerlake
device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
device pci 0d.2 off end # TBT DMA0 0x9A1B
device pci 0d.3 off end # TBT DMA1 0x9A1D
device pci 0e.0 on end # VMD 0x9A0B
device pci 0e.0 off end # VMD 0x9A0B
# From PCH EDS(576591)
device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7

2
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -160,7 +160,7 @@ chip soc/intel/tigerlake
device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
device pci 0d.2 off end # TBT DMA0 0x9A1B
device pci 0d.3 off end # TBT DMA1 0x9A1D
device pci 0e.0 on end # VMD 0x9A0B
device pci 0e.0 off end # VMD 0x9A0B
# From PCH EDS(576591)
device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7

7
src/soc/intel/tigerlake/fsp_params.c
View File

@ -214,6 +214,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
else
params->CnviMode = 0;
/* VMD */
dev = pcidev_path_on_root(SA_DEVFN_VMD);
if (dev)
params->VmdEnable = dev->enabled;
else
params->VmdEnable = 0;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

4
src/soc/intel/tigerlake/include/soc/pci_devs.h
View File

@ -54,6 +54,10 @@
#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2)
#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3)
#define SA_DEV_SLOT_VMD 0x0e
#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0)
#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0)
/* PCH Devices */
#define PCH_DEV_SLOT_SIO0 0x10
#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)