diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index aa93e47ed2..7393abcad5 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -190,8 +190,10 @@ void lpc_wideio_512_window(uint16_t base);
 void lpc_wideio_16_window(uint16_t base);
 u8 pm_read8(u8 reg);
 u16 pm_read16(u8 reg);
+u32 pm_read32(u8 reg);
 void pm_write8(u8 reg, u8 value);
 void pm_write16(u8 reg, u16 value);
+void pm_write32(u8 reg, u32 value);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ebda770be2..8377eca9b0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -58,6 +58,16 @@ u16 pm_read16(u8 reg)
 	return read16((void *)(PM_MMIO_BASE + reg));
 }
 
+void pm_write32(u8 reg, u32 value)
+{
+	write32((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u32 pm_read32(u8 reg)
+{
+	return read32((void *)(PM_MMIO_BASE + reg));
+}
+
 void sb_enable(device_t dev)
 {
 	printk(BIOS_DEBUG, "%s\n", __func__);