mb/google/nissa: Add devicetree
Fill in devicetree for nissa baseboard based on schematics. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kangheui Won
Felix Held
parent
ad8a2a475e
commit
168c25b82b
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@ -1,4 +1,148 @@
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chip soc/intel/alderlake
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_A"
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register "pmc_gpe0_dw1" = "GPP_H"
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register "pmc_gpe0_dw2" = "GPP_F"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# S0ix enable
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register "s0ix_enable" = "1"
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# Enable CNVi BT
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register "CnviBtCore" = "true"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
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register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
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register "PchHdaIDispCodecEnable" = "1"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C1 | Touchscreen |
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#| I2C2 | Sub-board(PSensor)/WCAM |
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#| I2C3 | Audio |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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}"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref tcss_xhci on end
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device ref xhci on end
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device ref shared_sram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end
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device ref heci1 on end
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device ref emmc on end
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device ref pcie_rp7 on
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# Enable SD Card PCIE 7 using clk 3
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end #PCIE7 SD card
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device ref uart0 on end
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device ref pch_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device ref hda on end
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end
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end
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