mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image. Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16). GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported. Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload. Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -201,6 +201,14 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
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}"
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# Set params for PEG 0:1:0
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register "Peg0MaxLinkWidth" = "Peg0_x16"
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# Configure PCIe clockgen in PCH
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# PEG0 uses SRCCLKREQ0 and CLKSRC0
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "0"
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register "PcieRpClkSrcNumber[0]" = "0"
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# Enable Root port 6(x1) for LAN.
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register "PcieRpEnable[5]" = "1"
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# Enable CLKREQ#
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