vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04. Changes include: - FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD BUG=b:254374913 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa. Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176 Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424 Reviewed-by: Reka Norman <rekanorman@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shaik Shahina
Felix Held
parent
b56a8d0272
commit
16ae1cf233
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@ -815,9 +815,11 @@ typedef struct {
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**/
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UINT8 PchFivrDynPm;
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/** Offset 0x0415 - Reserved
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/** Offset 0x0415 - FIVR VCCST ICCMax Control
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Enable/Disable FIVR VCCST ICCMax Control.
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$EN_DIS
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**/
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UINT8 Reserved10;
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UINT8 PchFivrVccstIccMaxControl;
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/** Offset 0x0416 - External V1P05 Icc Max Value
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Granularity of this setting is 1mA and maximal possible value is 500mA
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@ -844,7 +846,7 @@ typedef struct {
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/** Offset 0x041D - Reserved
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**/
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UINT8 Reserved11[3];
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UINT8 Reserved10[3];
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/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base
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Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
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@ -858,7 +860,7 @@ typedef struct {
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/** Offset 0x0428 - Reserved
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**/
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UINT8 Reserved12[12];
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UINT8 Reserved11[12];
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/** Offset 0x0434 - CNVi Configuration
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This option allows for automatic detection of Connectivity Solution. [Auto Detection]
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@ -869,7 +871,7 @@ typedef struct {
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/** Offset 0x0435 - Reserved
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**/
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UINT8 Reserved13;
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UINT8 Reserved12;
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/** Offset 0x0436 - CNVi BT Core
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Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
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@ -987,7 +989,7 @@ typedef struct {
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/** Offset 0x0455 - Reserved
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**/
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UINT8 Reserved14;
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UINT8 Reserved13;
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/** Offset 0x0456 - OS Timer
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16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
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@ -1023,7 +1025,7 @@ typedef struct {
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/** Offset 0x04AF - Reserved
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**/
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UINT8 Reserved15;
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UINT8 Reserved14;
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/** Offset 0x04B0 - PCIE RP Detect Timeout Ms
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The number of milliseconds within 0~65535 in reference code will wait for link to
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@ -1134,7 +1136,7 @@ typedef struct {
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/** Offset 0x0521 - Reserved
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**/
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UINT8 Reserved16[8];
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UINT8 Reserved15[8];
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/** Offset 0x0529 - Enable VMD controller
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Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
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@ -1193,7 +1195,7 @@ typedef struct {
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/** Offset 0x058D - Reserved
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**/
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UINT8 Reserved17[3];
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UINT8 Reserved16[3];
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/** Offset 0x0590 - VMD Variable
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VMD Variable Pointer.
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@ -1217,7 +1219,7 @@ typedef struct {
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/** Offset 0x05A0 - Reserved
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**/
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UINT8 Reserved18;
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UINT8 Reserved17;
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/** Offset 0x05A1 - Enable/Disable PMC-PD Solution
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This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
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@ -1272,7 +1274,7 @@ typedef struct {
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/** Offset 0x05B1 - Reserved
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**/
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UINT8 Reserved19;
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UINT8 Reserved18;
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/** Offset 0x05B2 - ITBT DMA LTR
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TCSS DMA1, DMA2 LTR value
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@ -1281,7 +1283,7 @@ typedef struct {
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/** Offset 0x05B6 - Reserved
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**/
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UINT8 Reserved20;
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UINT8 Reserved19;
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/** Offset 0x05B7 - Enable/Disable PTM
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This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
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@ -1306,7 +1308,7 @@ typedef struct {
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/** Offset 0x05C7 - Reserved
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**/
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UINT8 Reserved21;
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UINT8 Reserved20;
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/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
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Latency Tolerance Reporting, Snoop Latency Override Value.
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@ -1358,7 +1360,7 @@ typedef struct {
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/** Offset 0x05F3 - Reserved
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**/
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UINT8 Reserved22;
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UINT8 Reserved21;
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/** Offset 0x05F4 - Imon slope correction
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PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
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@ -1385,7 +1387,7 @@ typedef struct {
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/** Offset 0x0612 - Reserved
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**/
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UINT8 Reserved23[2];
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UINT8 Reserved22[2];
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/** Offset 0x0614 - Thermal Design Current time window
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PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
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@ -1434,7 +1436,7 @@ typedef struct {
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/** Offset 0x063B - Reserved
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**/
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UINT8 Reserved24;
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UINT8 Reserved23;
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/** Offset 0x063C - Thermal Design Current current limit
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PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
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@ -1503,7 +1505,7 @@ typedef struct {
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/** Offset 0x0687 - Reserved
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**/
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UINT8 Reserved25;
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UINT8 Reserved24;
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/** Offset 0x0688 - CpuBistData
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Pointer CPU BIST Data
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@ -1540,7 +1542,7 @@ typedef struct {
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/** Offset 0x0693 - Reserved
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**/
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UINT8 Reserved26;
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UINT8 Reserved25;
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/** Offset 0x0694 - VR Voltage Limit
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PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
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@ -1555,7 +1557,7 @@ typedef struct {
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/** Offset 0x06A0 - Reserved
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**/
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UINT8 Reserved27[7];
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UINT8 Reserved26[7];
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/** Offset 0x06A7 - VccIn Aux Imon slope correction
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PCODE MMIO Mailbox: VccIn Aux Imon slope correction. <b>0 - Auto</b> Specified in
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@ -1565,7 +1567,7 @@ typedef struct {
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/** Offset 0x06A8 - Reserved
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**/
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UINT8 Reserved28[2];
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UINT8 Reserved27[2];
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/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
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Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
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@ -1574,7 +1576,7 @@ typedef struct {
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/** Offset 0x06AB - Reserved
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**/
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UINT8 Reserved29[13];
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UINT8 Reserved28[13];
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/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
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Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
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@ -1597,7 +1599,7 @@ typedef struct {
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/** Offset 0x06BC - Reserved
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**/
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UINT8 Reserved30[2];
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UINT8 Reserved29[2];
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/** Offset 0x06BE - Min Voltage for C8
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PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
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@ -1631,7 +1633,7 @@ typedef struct {
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/** Offset 0x06C9 - Reserved
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**/
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UINT8 Reserved31;
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UINT8 Reserved30;
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/** Offset 0x06CA - CPU VR Power Delivery Design
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Used to communicate the power delivery design capability of the board. This value
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@ -1642,7 +1644,7 @@ typedef struct {
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/** Offset 0x06CB - Reserved
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**/
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UINT8 Reserved32[32];
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UINT8 Reserved31[32];
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/** Offset 0x06EB - Enable Power Optimizer
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Enable DMI Power Optimizer on PCH side.
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@ -1836,7 +1838,7 @@ typedef struct {
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/** Offset 0x0894 - Reserved
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**/
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UINT8 Reserved33;
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UINT8 Reserved32;
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/** Offset 0x0895 - Touch Host Controller Port 1 Assignment
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Assign THC Port 1
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@ -1846,7 +1848,7 @@ typedef struct {
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/** Offset 0x0896 - Reserved
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**/
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UINT8 Reserved34[2];
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UINT8 Reserved33[2];
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/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
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Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
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@ -1856,7 +1858,7 @@ typedef struct {
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/** Offset 0x089C - Reserved
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**/
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UINT8 Reserved35;
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UINT8 Reserved34;
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/** Offset 0x089D - PCIE RP Pcie Speed
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Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
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@ -1888,7 +1890,7 @@ typedef struct {
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/** Offset 0x0929 - Reserved
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**/
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UINT8 Reserved36[28];
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UINT8 Reserved35[28];
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/** Offset 0x0945 - PCIE RP Ltr Enable
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Latency Tolerance Reporting Mechanism.
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@ -1946,7 +1948,7 @@ typedef struct {
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/** Offset 0x09A1 - Reserved
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**/
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UINT8 Reserved37[3];
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UINT8 Reserved36[3];
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/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
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Allows to select the downstream port preset value that will be used during phase
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@ -2235,7 +2237,7 @@ typedef struct {
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/** Offset 0x0A45 - Reserved
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**/
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UINT8 Reserved38;
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UINT8 Reserved37;
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/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
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Custimized T0Level value.
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@ -2410,7 +2412,7 @@ typedef struct {
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/** Offset 0x0A6B - Reserved
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**/
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UINT8 Reserved39;
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UINT8 Reserved38;
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/** Offset 0x0A6C - Thermal Device Temperature
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Decides the temperature.
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@ -2435,7 +2437,7 @@ typedef struct {
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/** Offset 0x0A89 - Reserved
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**/
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UINT8 Reserved40[3];
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UINT8 Reserved39[3];
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/** Offset 0x0A8C - xHCI High Idle Time LTR override
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Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
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@ -2485,7 +2487,7 @@ typedef struct {
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/** Offset 0x0A9C - Reserved
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**/
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UINT8 Reserved41[4];
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UINT8 Reserved40[4];
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/** Offset 0x0AA0 - BgpdtHash[4]
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BgpdtHash values
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@ -2499,7 +2501,7 @@ typedef struct {
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/** Offset 0x0AC4 - Reserved
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**/
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UINT8 Reserved42[4];
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UINT8 Reserved41[4];
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/** Offset 0x0AC8 - BiosGuardModulePtr
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BiosGuardModulePtr default values
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@ -2532,7 +2534,7 @@ typedef struct {
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/** Offset 0x0ADB - Reserved
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**/
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UINT8 Reserved43;
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UINT8 Reserved42;
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/** Offset 0x0ADC - Change Default SVID
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Change the default SVID used in FSP to programming internal devices. This is only
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@ -2632,7 +2634,7 @@ typedef struct {
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/** Offset 0x0B00 - Reserved
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**/
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UINT8 Reserved44[12];
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UINT8 Reserved43[12];
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/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
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CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
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@ -2725,7 +2727,7 @@ typedef struct {
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/** Offset 0x0BD1 - Reserved
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**/
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UINT8 Reserved45[3];
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UINT8 Reserved44[3];
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/** Offset 0x0BD4 - CPU PCIE device override table pointer
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The PCIe device table is being used to override PCIe device ASPM settings. This
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@ -3002,7 +3004,7 @@ typedef struct {
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/** Offset 0x0CA2 - Reserved
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**/
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UINT8 Reserved46[2];
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UINT8 Reserved45[2];
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/** Offset 0x0CA4 - LogoPixelHeight Address
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Address of LogoPixelHeight
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@ -3016,7 +3018,7 @@ typedef struct {
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/** Offset 0x0CAC - Reserved
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**/
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UINT8 Reserved47[5];
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UINT8 Reserved46[5];
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/** Offset 0x0CB1 - RSR feature
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Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
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@ -3026,7 +3028,7 @@ typedef struct {
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/** Offset 0x0CB2 - Reserved
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**/
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UINT8 Reserved48[4];
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UINT8 Reserved47[4];
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/** Offset 0x0CB6 - Enable or Disable HWP
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Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
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@ -3419,7 +3421,7 @@ typedef struct {
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/** Offset 0x0D2D - Reserved
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**/
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UINT8 Reserved49;
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UINT8 Reserved48;
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/** Offset 0x0D2E - Platform Power Pmax
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PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
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@ -3459,7 +3461,7 @@ typedef struct {
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/** Offset 0x0D3A - Reserved
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**/
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UINT8 Reserved50[2];
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UINT8 Reserved49[2];
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/** Offset 0x0D3C - Package Long duration turbo mode power limit
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Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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@ -3562,7 +3564,7 @@ typedef struct {
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/** Offset 0x0D73 - Reserved
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**/
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UINT8 Reserved51[4];
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UINT8 Reserved50[4];
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/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
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Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
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@ -3634,7 +3636,7 @@ typedef struct {
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/** Offset 0x0D82 - Reserved
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**/
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UINT8 Reserved52;
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UINT8 Reserved51;
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/** Offset 0x0D83 - Dual Tau Boost
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Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
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@ -3645,7 +3647,7 @@ typedef struct {
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/** Offset 0x0D84 - Reserved
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**/
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UINT8 Reserved53[32];
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UINT8 Reserved52[32];
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/** Offset 0x0DA4 - End of Post message
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Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
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@ -3694,7 +3696,7 @@ typedef struct {
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/** Offset 0x0DAB - Reserved
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**/
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UINT8 Reserved54;
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UINT8 Reserved53;
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/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
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Latency Tolerance Reporting, Max Snoop Latency.
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@ -3846,7 +3848,7 @@ typedef struct {
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/** Offset 0x0F96 - Reserved
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**/
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UINT8 Reserved55[16];
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UINT8 Reserved54[16];
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/** Offset 0x0FA6 - FOMS Control Policy
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Choose the Foms Control Policy, <b>Default = 0 </b>
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@ -3868,7 +3870,7 @@ typedef struct {
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/** Offset 0x0FAF - Reserved
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**/
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UINT8 Reserved56[33];
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UINT8 Reserved55[33];
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/** Offset 0x0FD0 - FspEventHandler
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<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
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@ -3895,7 +3897,7 @@ typedef struct {
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/** Offset 0x0FD7 - Reserved
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**/
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UINT8 Reserved57;
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UINT8 Reserved56;
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/** Offset 0x0FD8 - Emmc Tx CMD Delay control register value
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Please see Tx CMD Delay Control register definition for help
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@ -3929,7 +3931,7 @@ typedef struct {
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/** Offset 0x0FF0 - Reserved
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**/
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UINT8 Reserved58[69];
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UINT8 Reserved57[69];
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/** Offset 0x1035 - Enable VMD Global Mapping
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Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
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@ -3939,7 +3941,7 @@ typedef struct {
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/** Offset 0x1036 - Reserved
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**/
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UINT8 Reserved59[138];
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UINT8 Reserved58[138];
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} FSP_S_CONFIG;
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/** Fsp S UPD Configuration
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@ -3960,7 +3962,7 @@ typedef struct {
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/** Offset 0x10C0
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**/
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UINT8 UnusedUpdSpace45[6];
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UINT8 UnusedUpdSpace44[6];
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/** Offset 0x10C6
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**/
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