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soc/mediatek/mt8195: Add mtcmos init support 

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Weiyi Lu 2021-02-09 17:59:26 +08:00 committed by Hung-Te Lin
parent 7fd932744e
commit 16bc621262
5 changed files with 137 additions and 0 deletions
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3
src/soc/mediatek/common/include/soc/mtcmos.h
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@ -8,8 +8,11 @@ struct power_domain_data {
u32 pwr_sta_mask;
u32 sram_pdn_mask;
u32 sram_ack_mask;
u32 caps;
};
#define SCPD_SRAM_ISO (1U << 0)
void mtcmos_audio_power_on(void);
void mtcmos_display_power_on(void);

6
src/soc/mediatek/common/mtcmos.c
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@ -33,6 +33,12 @@ static void mtcmos_power_on(const struct power_domain_data *pd)
while (read32(pd->pwr_con) & pd->sram_ack_mask)
continue;
if (pd->caps & SCPD_SRAM_ISO) {
setbits32(pd->pwr_con, SRAM_ISOINT_B);
udelay(1);
clrbits32(pd->pwr_con, SRAM_CKISO);
}
}
void mtcmos_display_power_on(void)

1
src/soc/mediatek/mt8195/Makefile.inc
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@ -35,6 +35,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c
ramstage-y += emi.c
ramstage-y += ../common/flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += soc.c
ramstage-y += ../common/timer.c timer.c

50
src/soc/mediatek/mt8195/include/soc/spm.h
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@ -4,8 +4,13 @@
#define SOC_MEDIATEK_MT8195_SPM_H
#include <soc/addressmap.h>
#include <soc/mtcmos.h>
#include <types.h>
/* SPM READ/WRITE CFG */
#define SPM_PROJECT_CODE 0xb16
#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
struct mtk_spm_regs {
u32 poweron_config_set;
u32 spm_power_on_val0;
@ -528,9 +533,54 @@ struct mtk_spm_regs {
u32 spm_pmsr_len_con2;
};
check_member(mtk_spm_regs, pwr_status, 0x016c);
check_member(mtk_spm_regs, audio_pwr_con, 0x0358);
check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c);
check_member(mtk_spm_regs, ulposc_con, 0x644);
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
static const struct power_domain_data disp[] = {
{
.pwr_con = &mtk_spm->vppsys0_pwr_con,
.pwr_sta_mask = 0x1 << 11,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
{
.pwr_con = &mtk_spm->vdosys0_pwr_con,
.pwr_sta_mask = 0x1 << 13,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
{
.pwr_con = &mtk_spm->vppsys1_pwr_con,
.pwr_sta_mask = 0x1 << 12,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
{
.pwr_con = &mtk_spm->vdosys1_pwr_con,
.pwr_sta_mask = 0x1 << 14,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
};
static const struct power_domain_data audio[] = {
{
.pwr_con = &mtk_spm->adsp_pwr_con,
.pwr_sta_mask = 0x1 << 10,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
.caps = SCPD_SRAM_ISO,
},
{
.pwr_con = &mtk_spm->audio_pwr_con,
.pwr_sta_mask = 0x1 << 8,
.sram_pdn_mask = 0x1 << 8,
.sram_ack_mask = 0x1 << 12,
},
};
#endif /* SOC_MEDIATEK_MT8195_SPM_H */

77
src/soc/mediatek/mt8195/mtcmos.c Normal file
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@ -0,0 +1,77 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <soc/infracfg.h>
#include <soc/mtcmos.h>
enum {
VPPSYS0_PROT_STEP_6_MASK = 0x00100000,
VPPSYS0_PROT_STEP_5_MASK = 0x0007F8FF,
VPPSYS0_PROT_STEP_4_MASK = 0x00800000,
VPPSYS0_PROT_STEP_3_MASK = 0x01600300,
VPPSYS0_PROT_STEP_2_MASK = 0x80381DC7,
VPPSYS0_PROT_STEP_1_MASK = 0x00000400,
VDOSYS0_PROT_STEP_5_MASK = 0x00200000,
VDOSYS0_PROT_STEP_4_MASK = 0x3FC00000,
VDOSYS0_PROT_STEP_3_MASK = 0x00000040,
VDOSYS0_PROT_STEP_2_MASK = 0x00800000,
VDOSYS0_PROT_STEP_1_MASK = 0x403E6238,
VPPSYS1_PROT_STEP_3_MASK = 0x000400C0,
VPPSYS1_PROT_STEP_2_MASK = 0x00800000,
VPPSYS1_PROT_STEP_1_MASK = 0x000001E0,
VDOSYS1_PROT_STEP_3_MASK = 0x00000400,
VDOSYS1_PROT_STEP_2_MASK = 0x00400000,
VDOSYS1_PROT_STEP_1_MASK = 0xC0000000,
AUDIO_PROT_STEP_1_MASK = 0x00000600,
};
void mtcmos_protect_display_bus(void)
{
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr,
VPPSYS0_PROT_STEP_6_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
VPPSYS0_PROT_STEP_5_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr,
VPPSYS0_PROT_STEP_4_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
VPPSYS0_PROT_STEP_3_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VPPSYS0_PROT_STEP_2_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr,
VPPSYS0_PROT_STEP_1_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr,
VDOSYS0_PROT_STEP_5_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VDOSYS0_PROT_STEP_4_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr,
VDOSYS0_PROT_STEP_3_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
VDOSYS0_PROT_STEP_2_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VDOSYS0_PROT_STEP_1_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
VPPSYS1_PROT_STEP_3_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VPPSYS1_PROT_STEP_2_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VPPSYS1_PROT_STEP_1_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
VDOSYS1_PROT_STEP_3_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VDOSYS1_PROT_STEP_2_MASK);
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
VDOSYS1_PROT_STEP_1_MASK);
}
void mtcmos_protect_audio_bus(void)
{
write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2,
AUDIO_PROT_STEP_1_MASK);
}