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soc/intel/alderlake: Hook up P2SB PCI ops 

P2SB device is being hidden from coreboot by FSP-S. This breaks the
resource allocator which does not report P2SB BAR via intel common
block P2SB driver. Hook up the common block P2SB driver ops to
soc_enable function so that the resources will be reported. The P2SB
device must be set as hidden in the devicetree.

This fixes the silent resource allocation conflicts on machines with
devices having big BARs which accidentally overlapped P2SB BAR.

TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big
BARs and see resource conflicts no longer occur.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c59441268676a8aab075abbc036e651b9426057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Michał Żygowski 2022-11-23 14:43:17 +01:00 committed by Felix Held
parent ffc4b8fda4
commit 16c7626077
2 changed files with 7 additions and 0 deletions
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5
src/soc/intel/alderlake/chip.c
View File

@ -16,6 +16,7 @@
#include <soc/hsphy.h> #include <soc/hsphy.h>
#include <soc/intel/common/vbt.h> #include <soc/intel/common/vbt.h>
#include <soc/itss.h> #include <soc/itss.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcie.h> #include <soc/pcie.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
@ -244,6 +245,7 @@ static struct device_operations cpu_bus_ops = {
static void soc_enable(struct device *dev) static void soc_enable(struct device *dev)
{ {
struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops;
/* /*
* Set the operations if it is a special bus type or a hidden PCI * Set the operations if it is a special bus type or a hidden PCI
* device. * device.
@ -255,6 +257,9 @@ static void soc_enable(struct device *dev)
else if (dev->path.type == DEVICE_PATH_PCI && else if (dev->path.type == DEVICE_PATH_PCI &&
dev->path.pci.devfn == PCH_DEVFN_PMC) dev->path.pci.devfn == PCH_DEVFN_PMC)
dev->ops = &pmc_ops; dev->ops = &pmc_ops;
else if (dev->path.type == DEVICE_PATH_PCI &&
dev->path.pci.devfn == PCH_DEVFN_P2SB)
dev->ops = soc_p2sb_ops;
else if (dev->path.type == DEVICE_PATH_GPIO) else if (dev->path.type == DEVICE_PATH_GPIO)
block_gpio_enable(dev); block_gpio_enable(dev);
} }

2
src/soc/intel/alderlake/include/soc/p2sb.h
View File

@ -14,4 +14,6 @@
#define PCH_P2SB_EPMASK0 0x220 #define PCH_P2SB_EPMASK0 0x220
extern const struct device_operations p2sb_ops;
#endif #endif