vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00
The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -454,9 +454,10 @@ typedef struct {
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UINT8 ApertureSize;
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/** Offset 0x01D0 - Board Type
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MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
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Halo, 7=UP Server
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0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
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MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC
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DDR5, 5=ULT/ULX/Mobile Halo, 7=UP Server
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0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 2:Desktop 2DPC DDR5, 5:ULT/ULX/Mobile Halo,
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7:UP Server
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**/
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UINT8 UserBd;
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@ -2939,12 +2940,12 @@ typedef struct {
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UINT8 Reserved38[3];
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/** Offset 0x08DE - REFRESH_PANIC_WM
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Refresh Panic Watermark, range 1-8, Default is 8
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DEPRECATED
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**/
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UINT8 RefreshPanicWm;
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/** Offset 0x08DF - REFRESH_HP_WM
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Refresh High Priority Watermark, range 1-7, Default is 7
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DEPRECATED
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**/
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UINT8 RefreshHpWm;
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@ -3161,7 +3162,7 @@ typedef struct {
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/** Offset 0x0AA8 - Reserved
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**/
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UINT8 Reserved46[56];
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UINT8 Reserved46[64];
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} FSP_M_CONFIG;
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/** Fsp M UPD Configuration
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@ -3180,11 +3181,11 @@ typedef struct {
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**/
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FSP_M_CONFIG FspmConfig;
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/** Offset 0x0AE0
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/** Offset 0x0AE8
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**/
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UINT8 UnusedUpdSpace29[6];
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/** Offset 0x0AE6
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/** Offset 0x0AEE
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**/
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UINT16 UpdTerminator;
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} FSPM_UPD;
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@ -1547,9 +1547,15 @@ typedef struct {
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**/
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UINT16 VrVoltageLimit[5];
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/** Offset 0x069E - Reserved
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/** Offset 0x069E - VccIn Aux Imon IccMax
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PCODE MMIO Mailbox: VccIn Aux Imon IccMax. <b>0 - Auto</b> Values are in 1/4 Amp
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increments. Range is 0-512.
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**/
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UINT8 Reserved27[12];
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UINT16 VccInAuxImonIccImax;
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/** Offset 0x06A0 - Reserved
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**/
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UINT8 Reserved27[10];
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/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
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Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
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@ -1960,8 +1966,8 @@ typedef struct {
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UINT8 PcieComplianceTestMode;
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/** Offset 0x09CA - PCIE Rp Function Swap
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Allows BIOS to use root port function number swapping when root port of function
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0 is disabled.
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DEPRECATED. Allows BIOS to use root port function number swapping when root port
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of function 0 is disabled.
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$EN_DIS
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**/
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UINT8 PcieRpFunctionSwap;
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@ -3861,7 +3867,7 @@ typedef struct {
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/** Offset 0x0FD5 - Reserved
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**/
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UINT8 Reserved57[3];
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UINT8 Reserved57[11];
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} FSP_S_CONFIG;
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/** Fsp S UPD Configuration
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@ -3880,11 +3886,11 @@ typedef struct {
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**/
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FSP_S_CONFIG FspsConfig;
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/** Offset 0x0FD8
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/** Offset 0x0FE0
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**/
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UINT8 UnusedUpdSpace40[6];
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/** Offset 0x0FDE
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/** Offset 0x0FE6
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**/
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UINT16 UpdTerminator;
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} FSPS_UPD;
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