GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Whitespace/typo/cosmetic fixes (trivial). 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-09-23 18:48:27 +00:00
parent d6b4f1cd0a
commit 16db6c3486
9 changed files with 48 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -51,7 +51,7 @@ Please consult http://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
-------------------------------------------------
------------------------------------------------
If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run

6
documentation/POSTCODES
View File

@ -2,13 +2,13 @@
coreboot POST Codes
-------------------------------------------------------------------------------
This is an (incomplete) list of POST codes emitted by coreboot v2.
This is an (incomplete) list of POST codes emitted by coreboot v4.
0x10 Entry into protected mode
0x01 Entry into 'crt0.s' reset code jumps to here
0x11 Start copying LinuxBIOS to RAM with decompression if compressed
0x11 Start copying coreboot to RAM with decompression if compressed
0x12 Copy/decompression finished jumping to RAM
0x80 Entry into LinuxBIOS in RAM
0x80 Entry into coreboot in RAM
0x13 Entry into c_start
0xfe Pre call to hardwaremain()
0x39 Console is initialized

27
src/Kconfig.deprecated_options
View File

@ -4,7 +4,7 @@
# It might be possible to consolidate hard_reset() to southbridges,
# given that it (usually) uses its registers.
# The long term goal would be to eliminate hard_reset from boards.
# The long term goal would be to eliminate hard_reset() from boards.
config BOARD_HAS_HARD_RESET
bool
default n
@ -20,7 +20,7 @@ config BOARD_HAS_FADT
help
This variable specifies whether a given board has a board-local
FADT in fadt.c. Long-term, those should be moved to appropriate
chipset components (eg. southbridge)
chipset components (eg. southbridge).
# There ought to be a better place to put data than code. Also, make this
# (or a similar) framework more universally usable, so all boards benefit
@ -32,17 +32,20 @@ config HAVE_BUS_CONFIG
This variable specifies whether a given board has a get_bus_conf.c
file containing information about bus routing.
# Will be removed (alongside with the PS2 init code) once payloads
# reliably support PS2 init themselves.
# Will be removed (alongside with the PS/2 init code) once payloads
# reliably support PS/2 init themselves.
config DRIVERS_PS2_KEYBOARD
bool "PS2 Keyboard init"
bool "PS/2 keyboard init"
default y
help
Enable this option to initialize PS2 keyboards found connected
to the PS2 port. Some payloads (eg, filo) require this
option. Other payloads (eg, SeaBIOS, Linux) do not require
it. Initializing a PS2 keyboard can take several hundred
milliseconds.
Enable this option to initialize PS/2 keyboards found connected
to the PS/2 port.
Some payloads (eg, filo) require this option. Other payloads
(eg, SeaBIOS, Linux) do not require it.
Initializing a PS/2 keyboard can take several hundred milliseconds.
If you know you will only use a payload which does not require
this option, then you can say "n" here to speed up boot time.
Otherwise say "y".
this option, then you can say N here to speed up boot time.
Otherwise say Y.

2
src/arch/i386/Kconfig
View File

@ -76,7 +76,7 @@ config UPDATE_IMAGE
default n
depends on TINY_BOOTBLOCK
help
If this option is activate, no new coreboot.rom file
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

4
src/cpu/amd/model_gx2/cache_as_ram.inc
View File

@ -184,7 +184,7 @@ done_cache_as_ram_main:
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
post_code(0x11) /* post 11 */
post_code(0x11)
/* TODO For suspend/resume the cache will have to live between
* CONFIG_RAMBASE and CONFIG_RAMTOP
@ -201,7 +201,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee) /* post fail ee */
post_code(0xee)
hlt
jmp .Lhlt

4
src/cpu/amd/model_lx/cache_as_ram.inc
View File

@ -210,7 +210,7 @@ done_cache_as_ram_main:
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
post_code(0x11) /* post 11 */
post_code(0x11)
/* TODO For suspend/resume the cache will have to live between
* CONFIG_RAMBASE and CONFIG_RAMTOP
@ -227,7 +227,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee) /* post fail ee */
post_code(0xee)
hlt
jmp .Lhlt

2
src/cpu/x86/32bit/entry32.inc
View File

@ -51,7 +51,7 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp
post_code(0x10) /* post 10 */
post_code(0x10)
movw $ROM_DATA_SEG, %ax
movw %ax, %ds

4
src/include/boot/coreboot_tables.h
View File

@ -74,10 +74,10 @@ struct lb_header
uint32_t table_entries;
};
/* Every entry in the boot enviroment list will correspond to a boot
/* Every entry in the boot environment list will correspond to a boot
* info record. Encoding both type and size. The type is obviously
* so you can tell what it is. The size allows you to skip that
* boot enviroment record if you don't know what it easy. This allows
* boot environment record if you don't know what it easy. This allows
* forward compatibility with records not yet defined.
*/
struct lb_record {

3
src/pc80/usbdebug_serial.c
View File

@ -1,6 +1,9 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.