Whitespace/typo/cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Uwe Hermann
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README
2
README
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@ -51,7 +51,7 @@ Please consult http://www.coreboot.org/Build_HOWTO for details.
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Testing coreboot Without Modifying Your Hardware
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-------------------------------------------------
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------------------------------------------------
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If you want to test coreboot without any risks before you really decide
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to use it on your hardware, you can use the QEMU system emulator to run
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@ -2,13 +2,13 @@
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coreboot POST Codes
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-------------------------------------------------------------------------------
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This is an (incomplete) list of POST codes emitted by coreboot v2.
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This is an (incomplete) list of POST codes emitted by coreboot v4.
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0x10 Entry into protected mode
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0x01 Entry into 'crt0.s' reset code jumps to here
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0x11 Start copying LinuxBIOS to RAM with decompression if compressed
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0x11 Start copying coreboot to RAM with decompression if compressed
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0x12 Copy/decompression finished jumping to RAM
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0x80 Entry into LinuxBIOS in RAM
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0x80 Entry into coreboot in RAM
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0x13 Entry into c_start
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0xfe Pre call to hardwaremain()
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0x39 Console is initialized
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@ -4,45 +4,48 @@
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# It might be possible to consolidate hard_reset() to southbridges,
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# given that it (usually) uses its registers.
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# The long term goal would be to eliminate hard_reset from boards.
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# The long term goal would be to eliminate hard_reset() from boards.
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config BOARD_HAS_HARD_RESET
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bool
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default n
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help
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This variable specifies whether a given board has a reset.c
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file containing a hard_reset() function.
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bool
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default n
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help
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This variable specifies whether a given board has a reset.c
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file containing a hard_reset() function.
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# It might be possible to consolidate FADTs to southbridges. This would
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# improve code reuse in the tree.
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config BOARD_HAS_FADT
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bool
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default n
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help
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This variable specifies whether a given board has a board-local
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FADT in fadt.c. Long-term, those should be moved to appropriate
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chipset components (eg. southbridge)
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bool
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default n
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help
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This variable specifies whether a given board has a board-local
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FADT in fadt.c. Long-term, those should be moved to appropriate
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chipset components (eg. southbridge).
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# There ought to be a better place to put data than code. Also, make this
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# (or a similar) framework more universally usable, so all boards benefit
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# from sharing data between the various tables.
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config HAVE_BUS_CONFIG
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bool
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default n
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bool
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default n
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help
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This variable specifies whether a given board has a get_bus_conf.c
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file containing information about bus routing.
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# Will be removed (alongside with the PS2 init code) once payloads
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# reliably support PS2 init themselves.
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# Will be removed (alongside with the PS/2 init code) once payloads
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# reliably support PS/2 init themselves.
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config DRIVERS_PS2_KEYBOARD
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bool "PS2 Keyboard init"
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bool "PS/2 keyboard init"
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default y
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help
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Enable this option to initialize PS2 keyboards found connected
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to the PS2 port. Some payloads (eg, filo) require this
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option. Other payloads (eg, SeaBIOS, Linux) do not require
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it. Initializing a PS2 keyboard can take several hundred
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milliseconds.
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Enable this option to initialize PS/2 keyboards found connected
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to the PS/2 port.
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Some payloads (eg, filo) require this option. Other payloads
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(eg, SeaBIOS, Linux) do not require it.
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Initializing a PS/2 keyboard can take several hundred milliseconds.
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If you know you will only use a payload which does not require
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this option, then you can say "n" here to speed up boot time.
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Otherwise say "y".
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this option, then you can say N here to speed up boot time.
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Otherwise say Y.
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@ -76,10 +76,10 @@ config UPDATE_IMAGE
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default n
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depends on TINY_BOOTBLOCK
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help
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If this option is activate, no new coreboot.rom file
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is created. Instead it is expected that there already
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is a suitable file for further processing.
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The bootblock will not be modified.
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If this option is enabled, no new coreboot.rom file
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is created. Instead it is expected that there already
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is a suitable file for further processing.
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The bootblock will not be modified.
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config ROMCC
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bool
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@ -184,7 +184,7 @@ done_cache_as_ram_main:
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11) /* post 11 */
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post_code(0x11)
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/* TODO For suspend/resume the cache will have to live between
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* CONFIG_RAMBASE and CONFIG_RAMTOP
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@ -201,7 +201,7 @@ __main:
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call copy_and_run
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.Lhlt:
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post_code(0xee) /* post fail ee */
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post_code(0xee)
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hlt
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jmp .Lhlt
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@ -210,7 +210,7 @@ done_cache_as_ram_main:
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11) /* post 11 */
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post_code(0x11)
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/* TODO For suspend/resume the cache will have to live between
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* CONFIG_RAMBASE and CONFIG_RAMTOP
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@ -227,7 +227,7 @@ __main:
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call copy_and_run
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.Lhlt:
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post_code(0xee) /* post fail ee */
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post_code(0xee)
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hlt
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jmp .Lhlt
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@ -51,7 +51,7 @@ __protected_start:
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/* Save the BIST value */
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movl %eax, %ebp
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post_code(0x10) /* post 10 */
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post_code(0x10)
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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@ -74,10 +74,10 @@ struct lb_header
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uint32_t table_entries;
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};
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/* Every entry in the boot enviroment list will correspond to a boot
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/* Every entry in the boot environment list will correspond to a boot
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* info record. Encoding both type and size. The type is obviously
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* so you can tell what it is. The size allows you to skip that
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* boot enviroment record if you don't know what it easy. This allows
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* boot environment record if you don't know what it easy. This allows
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* forward compatibility with records not yet defined.
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*/
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struct lb_record {
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@ -85,9 +85,9 @@ struct lb_record {
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uint32_t size; /* size of record (in bytes) */
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};
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#define LB_TAG_UNUSED 0x0000
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#define LB_TAG_UNUSED 0x0000
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#define LB_TAG_MEMORY 0x0001
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#define LB_TAG_MEMORY 0x0001
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struct lb_memory_range {
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struct lb_uint64 start;
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@ -108,7 +108,7 @@ struct lb_memory {
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struct lb_memory_range map[0];
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};
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#define LB_TAG_HWRPB 0x0002
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#define LB_TAG_HWRPB 0x0002
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struct lb_hwrpb {
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uint32_t tag;
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uint32_t size;
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@ -1,6 +1,9 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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