mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD TEST=Able to build and boot ADL-P RVP till ramstage early Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
parent
fb623a02c5
commit
16e410669a
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@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
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select DRIVERS_USB_ACPI
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select DRIVERS_SPI_ACPI
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select SOC_INTEL_ALDERLAKE
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select HAVE_SPD_IN_CBFS
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config CHROMEOS
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bool
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@ -1,11 +1,15 @@
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## SPDX-License-Identifier: GPL-2.0-only
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subdirs-y += spd
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage_fsp_params.c
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romstage-y += board_id.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boardid.h>
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#include <ec/acpi/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <stdint.h>
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#include <types.h>
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#include "board_id.h"
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static uint32_t get_board_id_via_ext_ec(void)
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{
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uint32_t id = BOARD_ID_INIT;
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if (google_chromeec_get_board_version(&id))
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id = BOARD_ID_UNKNOWN;
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return id;
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}
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/* Get Board ID via EC I/O port write/read */
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int get_board_id(void)
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{
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MAYBE_STATIC_NONZERO int id = -1;
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if (id < 0) {
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if (CONFIG(EC_GOOGLE_CHROMEEC)) {
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id = get_board_id_via_ext_ec();
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} else {
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if (send_ec_command(EC_FAB_ID_CMD) == 0) {
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id = recv_ec_data() << 8;
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id |= recv_ec_data();
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}
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}
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}
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return (id & BOARD_ID_MASK);
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}
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
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#define _MAINBOARD_COMMON_BOARD_ID_H_
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/* Board/FAB ID Command */
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#define EC_FAB_ID_CMD 0x0d
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/* Bit 5:0 for Board ID */
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#define BOARD_ID_MASK 0x3f
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/*
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* Returns board information (board id[15:8] and
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* Fab info[7:0]) on success and < 0 on error
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*/
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int get_board_id(void);
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#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <fsp/api.h>
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#include <soc/romstage.h>
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#include <spd_bin.h>
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#include <string.h>
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#include <soc/meminit.h>
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#include <baseboard/variants.h>
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#include <cbfs.h>
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#include "board_id.h"
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#define SPD_ID_MASK 0x7
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static size_t get_spd_index(void)
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{
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uint8_t board_id = get_board_id();
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size_t spd_index;
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printk(BIOS_INFO, "board id is 0x%x\n", board_id);
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spd_index = board_id & SPD_ID_MASK;
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printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index);
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return spd_index;
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}
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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const struct mb_cfg *mem_config = variant_memory_params();
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int board_id = get_board_id();
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const bool half_populated = false;
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const struct spd_info lpddr4_spd_info = {
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.read_type = READ_SPD_CBFS,
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.spd_spec.spd_index = get_spd_index(),
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};
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const struct spd_info ddr4_spd_info = {
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.read_type = READ_SMBUS,
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.spd_spec = {
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.spd_smbus_address = {
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[0] = 0xa0,
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[1] = 0xa2,
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[8] = 0xa4,
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[9] = 0xa6,
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},
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},
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};
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switch (board_id) {
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case ADL_P_DDR4_1:
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case ADL_P_DDR4_2:
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mupd->FspmConfig.DqPinsInterleaved = 1;
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memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated);
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break;
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case ADL_P_LP4_1:
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case ADL_P_LP4_2:
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mupd->FspmConfig.DqPinsInterleaved = 0;
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memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated);
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break;
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default:
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die("Unknown board id = 0x%x\n", board_id);
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break;
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}
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}
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@ -0,0 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-only
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SPD_SOURCES = adlrvp_lp4 #0b000
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SPD_SOURCES += empty # 0b001
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@ -0,0 +1,32 @@
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23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00
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48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -0,0 +1,32 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -1,3 +1,5 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += early_gpio.c
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romstage-y += memory.c
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@ -11,6 +11,36 @@ chip soc/intel/alderlake
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register "gen3_dec" = "0x00fc0901"
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register "gen4_dec" = "0x000c0081"
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register "PrmrrSize" = "0"
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# Enable PCH PCIE RP 5 using CLK 2
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register "PcieRpEnable[4]" = "1"
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register "PcieClkSrcClkReq[4]" = "4"
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register "PcieClkSrcUsage[2]" = "0x4"
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register "PcieRpClkReqDetect[4]" = "1"
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# Enable PCH PCIE RP 6 using CLK 5
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register "PcieRpEnable[5]" = "1"
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register "PcieClkSrcClkReq[5]" = "5"
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register "PcieClkSrcUsage[5]" = "0x5"
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register "PcieRpClkReqDetect[5]" = "1"
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# Enable PCH PCIE RP 9 using CLK 1
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register "PcieRpEnable[8]" = "1"
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register "PcieClkSrcClkReq[8]" = "8"
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register "PcieClkSrcUsage[1]" = "0x8"
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register "PcieRpClkReqDetect[8]" = "1"
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# Enable CPU PCIE RP 1 using PEG CLK 0
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register "PcieClkSrcUsage[0]" = "0x40"
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# Enable PCU PCIE PEG Slot 1 and 2
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register "PcieClkSrcUsage[3]" = "0x41"
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register "PcieClkSrcUsage[4]" = "0x42"
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# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
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register "PcieClkSrcUsage[6]" = "0xff"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Graphics
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@ -79,17 +109,17 @@ chip soc/intel/alderlake
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device pci 19.1 on end # I2C5
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device pci 19.2 on end # UART2
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device pci 1c.0 on end # RP1
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device pci 1c.1 on end # RP2
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device pci 1c.2 on end # RP3
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device pci 1c.3 on end # RP4
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device pci 1c.1 off end # RP2
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device pci 1c.2 off end # RP3
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device pci 1c.3 off end # RP4
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device pci 1c.4 on end # RP5
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device pci 1c.5 on end # RP6
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device pci 1c.6 on end # RP7
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device pci 1c.7 on end # RP8
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device pci 1c.6 off end # RP7
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device pci 1c.7 off end # RP8
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device pci 1d.0 on end # RP9
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device pci 1d.1 on end # RP10
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device pci 1d.2 on end # RP11
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device pci 1d.3 on end # RP12
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device pci 1d.1 off end # RP10
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device pci 1d.2 off end # RP11
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device pci 1d.3 off end # RP12
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device pci 1e.0 off end # UART0
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device pci 1e.1 off end # UART1
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device pci 1e.2 off end # GSPI0
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@ -0,0 +1,52 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cpu.h>
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#include "../../board_id.h"
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#include <baseboard/variants.h>
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#include <soc/romstage.h>
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static const struct mb_cfg mem_config = {
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/* DQ byte map */
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.dq_map = {
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{ 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */
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10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */
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{ 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */
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5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */
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{ 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */
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12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */
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{ 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */
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9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */
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{ 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */
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10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */
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{ 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */
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3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */
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{ 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */
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7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */
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{ 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */
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13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */
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},
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/* DQS CPU<>DRAM map */
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.dqs_map = {
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/* Ch 0 1 2 3 */
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{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 },
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{ 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }
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},
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/* Baseboard uses only 100ohm Rcomp resistors */
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.rcomp_resistor = {100, 100, 100},
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/*
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* Baseboard Rcomp target values.
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*/
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.rcomp_targets = {40, 30, 33, 33, 30},
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.ect = true, /* Early Command Training */
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.UserBd = BOARD_TYPE_MOBILE,
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};
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const struct mb_cfg *variant_memory_params(void)
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{
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return &mem_config;
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}
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@ -4,13 +4,25 @@
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#define __BASEBOARD_VARIANTS_H__
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#include <soc/gpio.h>
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#include <soc/meminit.h>
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#include <stdint.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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enum adl_boardid {
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/* ADL-P LPDDR4 RVPs */
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ADL_P_LP4_1 = 0x10,
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ADL_P_LP4_2 = 0x11,
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/* ADL-P DDR4 RVPs */
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ADL_P_DDR4_1 = 0x14,
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ADL_P_DDR4_2 = 0x3F,
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};
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/* The next set of functions return the gpio table and fill in the number of
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* entries for each table. */
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const struct cros_gpio *variant_cros_gpios(size_t *num);
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void variant_configure_early_gpio_pads(void);
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size_t variant_memory_sku(void);
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const struct mb_cfg *variant_memory_params(void);
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#endif /*__BASEBOARD_VARIANTS_H__ */
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