soc/amd/cezanne: Use common fsp-s preloader

Use the common preloader for fsp-s

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Fred Reitberger 2023-01-11 15:10:30 -05:00 committed by Felix Held
parent 330a7b5c2c
commit 16f55f237c
3 changed files with 1 additions and 12 deletions

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@ -66,6 +66,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2 select SSE2
select UDK_2017_BINDING select UDK_2017_BINDING
select USE_DDR4 select USE_DDR4

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@ -37,7 +37,6 @@ ramstage-y += gpio.c
ramstage-y += graphics.c ramstage-y += graphics.c
ramstage-y += i2c.c ramstage-y += i2c.c
ramstage-y += mca.c ramstage-y += mca.c
ramstage-y += preload.c
ramstage-y += reset.c ramstage-y += reset.c
ramstage-y += root_complex.c ramstage-y += root_complex.c
ramstage-y += uart.c ramstage-y += uart.c

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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <fsp/api.h>
static void start_fsps_preload(void *unused)
{
preload_fsps();
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);