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amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes 

Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12712
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson 2015-12-11 12:58:07 -06:00 committed by Martin Roth
parent ed4aa043c6
commit 16ff807ba6
2 changed files with 12 additions and 12 deletions
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18
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -737,16 +737,16 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev); pci_domain_read_resources(dev);
#if CONFIG_MMCONF_SUPPORT if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) {
struct resource *res = new_resource(dev, 0xc0010058); struct resource *res = new_resource(dev, 0xc0010058);
res->base = CONFIG_MMCONF_BASE_ADDRESS; res->base = CONFIG_MMCONF_BASE_ADDRESS;
res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
#endif }
if (is_fam15h()) { if (is_fam15h()) {
enable_cc6 = 0; enable_cc6 = 0;

6
src/southbridge/amd/sr5650/ht.c
View File

@ -157,8 +157,8 @@ static void sr5690_read_resource(struct device *dev)
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* rpr6.2.(1). Write the Base Address Register (BAR) */ /* rpr6.2.(1). Write the Base Address Register (BAR) */
pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */
compact_resources(dev); compact_resources(dev);
} }
@ -166,7 +166,7 @@ static void sr5690_read_resource(struct device *dev)
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
static void sr5690_set_resources(struct device *dev) static void sr5690_set_resources(struct device *dev)
{ {
pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
} }