update atom car code in the same way that 6ex/6fx was updated.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
6d1b0d84f2
commit
170679b9dd
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@ -35,8 +35,6 @@ cache_as_ram:
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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post_code(0x21)
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/* Zero out all Fixed Range and Variable Range MTRRs */
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movl $mtrr_table, %esi
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movl $( (mtrr_table_end - mtrr_table) / 2), %edi
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@ -49,7 +47,6 @@ clear_mtrrs:
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add $2, %esi
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dec %edi
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jnz clear_mtrrs
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post_code(0x22)
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/* Configure the default memory type to uncacheable */
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movl $MTRRdefType_MSR, %ecx
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@ -57,42 +54,36 @@ clear_mtrrs:
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(0x23)
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/* Set cache as ram base address */
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movl $(MTRRphysBase_MSR(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x24)
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/* Set cache as ram mask */
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movl $(MTRRphysMask_MSR(0)), %ecx
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movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x25)
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/* Enable MTRR */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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wrmsr
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post_code(0x26)
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/* Enable L2 Cache */
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movl $0x11e, %ecx
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rdmsr
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orl $(1 << 8), %eax
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wrmsr
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post_code(0x27)
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/* CR0.CD = 0, CR0.NW = 0 */
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movl %cr0, %eax
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andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
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invd
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movl %eax, %cr0
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post_code(0x28)
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/* Clear the cache memory reagion */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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@ -101,7 +92,6 @@ clear_mtrrs:
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xorl %eax, %eax
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rep stosl
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post_code(0x29)
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/* Enable Cache As RAM mode by disabling cache */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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@ -110,7 +100,7 @@ clear_mtrrs:
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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xorl %edx, %edx
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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@ -126,7 +116,6 @@ clear_mtrrs:
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wrmsr
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#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
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post_code(0x2a)
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/* enable cache */
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movl %cr0, %eax
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andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
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@ -148,12 +137,143 @@ clear_mtrrs:
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post_code(0x23)
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call stage1_main
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/* Call romstage.c main function */
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call main
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post_code(0x2f)
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error:
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post_code(0x30)
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/* Disable Cache */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~(1 << 11)), %eax
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wrmsr
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post_code(0x31)
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invd
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#if 0
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xorl %eax, %eax
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xorl %edx, %edx
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movl $MTRRphysBase_MSR(0), %ecx
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wrmsr
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movl $MTRRphysMask_MSR(0), %ecx
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wrmsr
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movl $MTRRphysBase_MSR(1), %ecx
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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wrmsr
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#endif
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post_code(0x33)
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#undef CLEAR_FIRST_1M_RAM
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#ifdef CLEAR_FIRST_1M_RAM
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post_code(0x34)
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/* Enable Write Combining and Speculative Reads for the first 1MB */
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movl $MTRRphysBase_MSR(0), %ecx
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movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRRphysMask_MSR(0), %ecx
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movl $(~(1024*1024 -1) | (1 << 11)), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x35)
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#endif
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/* Enable Cache */
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movl %cr0, %eax
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andl $~( (1 << 30) | (1 << 29) ), %eax
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movl %eax, %cr0
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post_code(0x36)
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#ifdef CLEAR_FIRST_1M_RAM
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/* Clear first 1MB of RAM */
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movl $0x00000000, %edi
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cld
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xorl %eax, %eax
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movl $((1024*1024) / 4), %ecx
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rep stosl
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post_code(0x37)
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#endif
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/* Disable Cache */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Enable Write Back and Speculative Reads for the first 1MB */
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movl $MTRRphysBase_MSR(0), %ecx
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movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRRphysMask_MSR(0), %ecx
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movl $(~(1024*1024 -1) | (1 << 11)), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x39)
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/* And Enable Cache again after setting MTRRs */
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movl %cr0, %eax
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andl $~( (1 << 30) | (1 << 29) ), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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wrmsr
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post_code(0x3b)
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/* Invalidate the cache again */
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invd
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post_code(0x3c)
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11)
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cld /* clear direction flag */
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movl %ebp, %esi
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/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
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* makes sure that we stay completely within the 1M-64K of memory that we
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* preserve for suspend/resume.
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*/
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#ifndef HIGH_MEMORY_SAVE
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#warning Need a central place for HIGH_MEMORY_SAVE
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#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
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#endif
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movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp
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movl %esp, %ebp
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pushl %esi
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call copy_and_run
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.Lhlt:
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post_code(0xee)
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hlt
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jmp error
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jmp .Lhlt
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mtrr_table:
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/* Fixed MTRRs */
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@ -1,94 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* called from assembler code */
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void stage1_main(unsigned long bist);
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/* from romstage.c */
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void real_main(unsigned long bist);
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void stage1_main(unsigned long bist)
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{
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unsigned int cpu_reset = 0;
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real_main(bist);
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/* No servicable parts below this line .. */
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{
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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"movl %%esp, %0\n\t"
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: "=a" (v_esp)
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);
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printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
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}
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printk(BIOS_SPEW, "cpu_reset = %08x\n",cpu_reset);
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if(cpu_reset == 0) {
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print_spew("Clearing initial memory region: ");
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}
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print_spew("No cache as ram now - ");
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/* store cpu_reset to ebx */
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__asm__ volatile (
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"movl %0, %%ebx\n\t"
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::"a" (cpu_reset)
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);
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if(cpu_reset==0) {
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#define CLEAR_FIRST_1M_RAM 1
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#include "cache_as_ram_post.c"
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} else {
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#undef CLEAR_FIRST_1M_RAM
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#include "cache_as_ram_post.c"
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}
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__asm__ volatile (
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/* set new esp */
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"movl %0, %%ebp\n\t"
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"movl %0, %%esp\n\t"
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::"a"( CONFIG_RAMBASE + (1024-64)*1024 )
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);
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{
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unsigned new_cpu_reset;
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/* get back cpu_reset from ebx */
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__asm__ volatile (
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"movl %%ebx, %0\n\t"
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:"=a" (new_cpu_reset)
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);
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#ifdef CONFIG_DEACTIVATE_CAR
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print_debug("Deactivating CAR");
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#include CONFIG_DEACTIVATE_CAR_FILE
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print_debug(" - Done.\n");
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#endif
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/* Copy and execute coreboot_ram */
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copy_and_run(new_cpu_reset);
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/* We will not return */
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}
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print_debug("sorry. parachute did not open.\n");
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}
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@ -1,123 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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__asm__ volatile (
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"movb $0x30, %al\noutb %al, $0x80\n"
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/* Disable Cache */
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"movl %cr0, %eax\n"
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"orl $(1 << 30), %eax\n"
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"movl %eax, %cr0\n"
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"movb $0x31, %al\noutb %al, $0x80\n"
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/* Disable MTRR */
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"movl $MTRRdefType_MSR, %ecx\n"
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"rdmsr\n"
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"andl $(~(1 << 11)), %eax\n"
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"wrmsr\n"
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"movb $0x32, %al\noutb %al, $0x80\n"
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"invd\n"
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#if 0
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"xorl %eax, %eax\n"
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"xorl %edx, %edx\n"
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"movl $MTRRphysBase_MSR(0), %ecx\n"
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"wrmsr\n"
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"movl $MTRRphysMask_MSR(0), %ecx\n"
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"wrmsr\n"
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"movl $MTRRphysBase_MSR(1), %ecx\n"
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"wrmsr\n"
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"movl $MTRRphysMask_MSR(1), %ecx\n"
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"wrmsr\n"
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#endif
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"movb $0x33, %al\noutb %al, $0x80\n"
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#ifdef CLEAR_FIRST_1M_RAM
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"movb $0x34, %al\noutb %al, $0x80\n"
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/* Enable Write Combining and Speculative Reads for the first 1MB */
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"movl $MTRRphysBase_MSR(0), %ecx\n"
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"movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n"
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"xorl %edx, %edx\n"
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"wrmsr\n"
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"movl $MTRRphysMask_MSR(0), %ecx\n"
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"movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
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"xorl %edx, %edx\n"
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"wrmsr\n"
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"movb $0x35, %al\noutb %al, $0x80\n"
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#endif
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/* Enable Cache */
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"movl %cr0, %eax\n"
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"andl $~( (1 << 30) | (1 << 29) ), %eax\n"
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"movl %eax, %cr0\n"
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"movb $0x36, %al\noutb %al, $0x80\n"
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#ifdef CLEAR_FIRST_1M_RAM
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/* Clear first 1MB of RAM */
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"movl $0x00000000, %edi\n"
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"cld\n"
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"xorl %eax, %eax\n"
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"movl $((1024*1024) / 4), %ecx\n"
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"rep stosl\n"
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"movb $0x37, %al\noutb %al, $0x80\n"
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#endif
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/* Disable Cache */
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"movl %cr0, %eax\n"
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"orl $(1 << 30), %eax\n"
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"movl %eax, %cr0\n"
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"movb $0x38, %al\noutb %al, $0x80\n"
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/* Enable Write Back and Speculative Reads for the first 1MB */
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"movl $MTRRphysBase_MSR(0), %ecx\n"
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"movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n"
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"xorl %edx, %edx\n"
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"wrmsr\n"
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"movl $MTRRphysMask_MSR(0), %ecx\n"
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"movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
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"xorl %edx, %edx\n"
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"wrmsr\n"
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"movb $0x39, %al\noutb %al, $0x80\n"
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/* And Enable Cache again after setting MTRRs */
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"movl %cr0, %eax\n"
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"andl $~( (1 << 30) | (1 << 29) ), %eax\n"
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"movl %eax, %cr0\n"
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"movb $0x3a, %al\noutb %al, $0x80\n"
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/* Enable MTRR */
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"movl $MTRRdefType_MSR, %ecx\n"
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"rdmsr\n"
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"orl $(1 << 11), %eax\n"
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"wrmsr\n"
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"movb $0x3b, %al\noutb %al, $0x80\n"
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/* Invalidate the cache again */
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"invd\n"
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"movb $0x3c, %al\noutb %al, $0x80\n"
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);
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@ -223,9 +223,7 @@ static void early_ich7_init(void)
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//
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#include "lib/cbmem.c"
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#include "cpu/intel/model_106cx/cache_as_ram_disable.c"
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void real_main(unsigned long bist)
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void main(unsigned long bist)
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{
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u32 reg32;
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int boot_mode = 0;
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