add ram resources
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -37,6 +37,24 @@ static inline unsigned int fls(unsigned int x)
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return r;
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}
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/* sdram parameters for OLPC:
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row address = 13
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col address = 9
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banks = 4
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dimm0size=128MB
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d0_MB=1 (module banks)
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d0_cb=4 (component banks)
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do_psz=4KB (page size)
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Trc=10 (clocks)
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Tras=7
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Trcd=3
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Trp=3
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Trrd=2
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Tref=17.8ms
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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@ -50,21 +68,17 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = spd_read_byte(0xA0, 5);
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if (module_banks < 1 || module_banks > 2)
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print_err("Module banks per dimm\r\n");
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module_banks = 1;
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = spd_read_byte(0xA0, 17);
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if (val < 2 || val > 4)
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print_err("Component banks per module bank\r\n");
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val = 4;
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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HERE
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/* get the module bank density, SPD byte 31 */
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val = spd_read_byte(0xA0, 31);
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val = fls(val);
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@ -236,10 +236,11 @@ setup_gx2(void)
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static void optimize_xbus(device_t dev)
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{
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/* Optimise X-Bus performance */
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pci_write_config8(dev, 0x40, 0x1e);
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/* pci_write_config8(dev, 0x40, 0x1e);
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pci_write_config8(dev, 0x41, 0x52);
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pci_write_config8(dev, 0x43, 0xc1);
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pci_write_config8(dev, 0x44, 0x00);
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*/
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}
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static void enable_shadow(device_t dev)
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@ -433,6 +434,7 @@ static void enable_dev(struct device *dev)
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do_vsmbios();
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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ram_resource(dev, 0, 0, sizeram()*1024);
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} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
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