GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mediatek: Share PLL code among similar SOCs 

Refactor PLL code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27305
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tristan Shieh 2018-07-02 17:20:13 +08:00 committed by Patrick Georgi
parent bb684e0c8d
commit 17180af69a
6 changed files with 341 additions and 246 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
src/soc/mediatek/common/include/soc/pll_common.h Normal file
View File

@ -0,0 +1,73 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_MEDIATEK_PLL_COMMON_H
#define SOC_MEDIATEK_PLL_COMMON_H
#include <soc/addressmap.h>
#include <types.h>
/* These need to be macros for use in static initializers. */
#define mtk_topckgen ((struct mtk_topckgen_regs *)CKSYS_BASE)
#define mtk_apmixed ((struct mtk_apmixed_regs *)APMIXED_BASE)
#define PLL_PWR_ON (1 << 0)
#define PLL_EN (1 << 0)
#define PLL_ISO (1 << 1)
#define PLL_RSTB_SHIFT (24)
#define NO_RSTB_SHIFT (255)
#define PLL_PCW_CHG (1 << 31)
#define PLL_POSTDIV_MASK 0x7
struct mux {
void *reg;
void *upd_reg;
u8 mux_shift;
u8 mux_width;
u8 upd_shift;
};
struct pll {
void *reg;
void *pwr_reg;
void *div_reg;
void *pcw_reg;
const u32 *div_rate;
u8 rstb_shift;
u8 pcwbits;
u8 div_shift;
u8 pcw_shift;
};
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \
_pcw_reg, _pcw_shift, _div_rate) \
[_id] = { \
.reg = &mtk_apmixed->_reg, \
.pwr_reg = &mtk_apmixed->_pwr_reg, \
.rstb_shift = _rstb, \
.pcwbits = _pcwbits, \
.div_reg = &mtk_apmixed->_div_reg, \
.div_shift = _div_shift, \
.pcw_reg = &mtk_apmixed->_pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_rate = _div_rate, \
}
void pll_set_pcw_change(const struct pll *pll);
void mux_set_sel(const struct mux *mux, u32 sel);
int pll_set_rate(const struct pll *pll, u32 rate);
void mt_pll_init(void);
#endif

88
src/soc/mediatek/common/pll.c Normal file
View File

@ -0,0 +1,88 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <assert.h>
#include <soc/pll.h>
#define GENMASK(h, l) (BIT(h + 1) - BIT(l))
void mux_set_sel(const struct mux *mux, u32 sel)
{
u32 mask = GENMASK(mux->mux_width - 1, 0);
u32 val = read32(mux->reg);
val &= ~(mask << mux->mux_shift);
val |= (sel & mask) << mux->mux_shift;
write32(mux->reg, val);
if (mux->upd_reg)
write32(mux->upd_reg, 1 << mux->upd_shift);
}
static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,
u32 freq)
{
const u32 fin_hz = CLK26M_HZ;
const u32 *div_rate = pll->div_rate;
u32 val;
assert(freq <= div_rate[0]);
assert(freq >= 1 * GHz / 16);
for (val = 1; div_rate[val] != 0; val++) {
if (freq > div_rate[val])
break;
}
val--;
*postdiv = val;
/* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */
val += pll->pcwbits - PCW_INTEGER_BITS;
*pcw = ((u64)freq << val) / fin_hz;
}
static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv)
{
u32 val;
/* set postdiv */
val = read32(pll->div_reg);
val &= ~(PLL_POSTDIV_MASK << pll->div_shift);
val |= postdiv << pll->div_shift;
/* set postdiv and pcw at the same time if on the same register */
if (pll->div_reg != pll->pcw_reg) {
write32(pll->div_reg, val);
val = read32(pll->pcw_reg);
}
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
write32(pll->pcw_reg, val);
pll_set_pcw_change(pll);
}
int pll_set_rate(const struct pll *pll, u32 rate)
{
u32 pcw, postdiv;
pll_calc_values(pll, &pcw, &postdiv, rate);
pll_set_rate_regs(pll, pcw, postdiv);
return 0;
}

6
src/soc/mediatek/mt8173/Makefile.inc
View File

@ -18,7 +18,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
bootblock-y += bootblock.c bootblock-y += bootblock.c
bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
bootblock-y += i2c.c bootblock-y += i2c.c
bootblock-y += pll.c bootblock-y += ../common/pll.c pll.c
bootblock-y += spi.c bootblock-y += spi.c
bootblock-y += ../common/timer.c bootblock-y += ../common/timer.c
bootblock-y += timer.c bootblock-y += timer.c
@ -47,7 +47,7 @@ verstage-y += gpio.c
################################################################################ ################################################################################
romstage-$(CONFIG_SPI_FLASH) += flash_controller.c romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
romstage-y += pll.c romstage-y += ../common/pll.c pll.c
romstage-y += ../common/timer.c romstage-y += ../common/timer.c
romstage-y += timer.c romstage-y += timer.c
@ -75,7 +75,7 @@ ramstage-y += mt6311.c
ramstage-y += da9212.c ramstage-y += da9212.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-y += ../common/wdt.c ramstage-y += ../common/wdt.c
ramstage-y += pll.c ramstage-y += ../common/pll.c pll.c
ramstage-y += rtc.c ramstage-y += rtc.c
ramstage-y += usb.c ramstage-y += usb.c

4
src/soc/mediatek/mt8173/dramc_pi_basic_api.c
View File

@ -738,7 +738,7 @@ void transfer_to_spm_control(void)
u32 msk; u32 msk;
msk = BIT(7) | BIT(11) | BIT(15); msk = BIT(7) | BIT(11) | BIT(15);
clrbits_le32(&mt8173_apmixed->ap_pll_con3, msk); clrbits_le32(&mtk_apmixed->ap_pll_con3, msk);
msk = BIT(0) | BIT(4) | BIT(8); msk = BIT(0) | BIT(4) | BIT(8);
clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk);
@ -756,7 +756,7 @@ void transfer_to_reg_control(void)
u32 val; u32 val;
val = BIT(7) | BIT(11) | BIT(15); val = BIT(7) | BIT(11) | BIT(15);
setbits_le32(&mt8173_apmixed->ap_pll_con3, val); setbits_le32(&mtk_apmixed->ap_pll_con3, val);
val = BIT(0) | BIT(4) | BIT(8); val = BIT(0) | BIT(4) | BIT(8);
setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val);

32
src/soc/mediatek/mt8173/include/soc/pll.h
View File

@ -17,9 +17,9 @@
#define SOC_MEDIATEK_MT8173_PLL_H #define SOC_MEDIATEK_MT8173_PLL_H
#include <soc/emi.h> #include <soc/emi.h>
#include <soc/addressmap.h> #include <soc/pll_common.h>
struct mt8173_topckgen_regs { struct mtk_topckgen_regs {
u32 clk_mode; u32 clk_mode;
u32 dcm_cfg; u32 dcm_cfg;
u32 reserved1[6]; u32 reserved1[6];
@ -97,12 +97,12 @@ struct mt8173_topckgen_regs {
u32 mbist_cfg_3; /* 0x314 */ u32 mbist_cfg_3; /* 0x314 */
}; };
check_member(mt8173_topckgen_regs, clk_cfg_0, 0x40); check_member(mtk_topckgen_regs, clk_cfg_0, 0x40);
check_member(mt8173_topckgen_regs, clk_cfg_8, 0x100); check_member(mtk_topckgen_regs, clk_cfg_8, 0x100);
check_member(mt8173_topckgen_regs, clk_scp_cfg_0, 0x200); check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200);
check_member(mt8173_topckgen_regs, mbist_cfg_3, 0x314); check_member(mtk_topckgen_regs, mbist_cfg_3, 0x314);
struct mt8173_apmixed_regs { struct mtk_apmixed_regs {
u32 ap_pll_con0; u32 ap_pll_con0;
u32 reserved1[1]; u32 reserved1[1];
u32 ap_pll_con2; /* 0x008 */ u32 ap_pll_con2; /* 0x008 */
@ -187,12 +187,19 @@ struct mt8173_apmixed_regs {
u32 msdcpll2_pwr_con0; /* 0x2fc */ u32 msdcpll2_pwr_con0; /* 0x2fc */
}; };
check_member(mt8173_apmixed_regs, ap_pll_con2, 0x8); check_member(mtk_apmixed_regs, ap_pll_con2, 0x8);
check_member(mt8173_apmixed_regs, armca15pll_con0, 0x200); check_member(mtk_apmixed_regs, armca15pll_con0, 0x200);
check_member(mt8173_apmixed_regs, msdcpll2_pwr_con0, 0x2fc); check_member(mtk_apmixed_regs, msdcpll2_pwr_con0, 0x2fc);
static struct mt8173_topckgen_regs *const mt8173_topckgen = (void *)CKSYS_BASE; enum {
static struct mt8173_apmixed_regs *const mt8173_apmixed = (void *)APMIXED_BASE; PLL_PWR_ON_DELAY = 5,
PLL_ISO_DELAY = 0,
PLL_EN_DELAY = 40,
};
enum {
PCW_INTEGER_BITS = 7,
};
/* PLL rate */ /* PLL rate */
enum { enum {
@ -283,7 +290,6 @@ enum {
}; };
void mt_pll_post_init(void); void mt_pll_post_init(void);
void mt_pll_init(void);
void mt_pll_set_aud_div(u32 rate); void mt_pll_set_aud_div(u32 rate);
void mt_pll_enable_ssusb_clk(void); void mt_pll_enable_ssusb_clk(void);
void mt_pll_raise_ca53_freq(u32 freq); void mt_pll_raise_ca53_freq(u32 freq);

384
src/soc/mediatek/mt8173/pll.c
View File

@ -15,7 +15,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <assert.h> #include <assert.h>
#include <console/console.h>
#include <delay.h> #include <delay.h>
#include <stddef.h> #include <stddef.h>
@ -23,8 +22,6 @@
#include <soc/infracfg.h> #include <soc/infracfg.h>
#include <soc/pll.h> #include <soc/pll.h>
#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
enum mux_id { enum mux_id {
TOP_AXI_SEL, TOP_AXI_SEL,
TOP_MEM_SEL, TOP_MEM_SEL,
@ -68,20 +65,13 @@ enum mux_id {
TOP_NR_MUX TOP_NR_MUX
}; };
#define TOPCKGEN_REG(x) (CKSYS_BASE + offsetof(struct mt8173_topckgen_regs, x))
#define APMIXED_REG(x) (APMIXED_BASE + offsetof(struct mt8173_apmixed_regs, x))
struct mux {
void *reg;
u8 mux_shift;
u8 mux_width;
};
#define MUX(_id, _reg, _mux_shift, _mux_width) \ #define MUX(_id, _reg, _mux_shift, _mux_width) \
[_id] = { \ [_id] = { \
.reg = (void *)TOPCKGEN_REG(_reg), \ .reg = &mtk_topckgen->_reg, \
.mux_shift = _mux_shift, \ .mux_shift = _mux_shift, \
.mux_width = _mux_width, \ .mux_width = _mux_width, \
.upd_reg = NULL, \
.upd_shift = 0, \
} }
static const struct mux muxes[] = { static const struct mux muxes[] = {
@ -136,23 +126,62 @@ static const struct mux muxes[] = {
MUX(TOP_RTC_SEL, clk_cfg_13, 24, 2), MUX(TOP_RTC_SEL, clk_cfg_13, 24, 2),
}; };
static void mux_set_sel(const struct mux *mux, u32 sel) struct mux_sel {
{ enum mux_id id;
u32 mask = GENMASK(mux->mux_width - 1, 0); u32 sel;
u32 val = read32(mux->reg); };
val &= ~(mask << mux->mux_shift); static const struct mux_sel mux_sels[] = {
val |= (sel & mask) << mux->mux_shift; /* CLK_CFG_0 */
write32(mux->reg, val); { .id = TOP_AXI_SEL, .sel = 5 }, /* 5: univpll2_d2 */
} { .id = TOP_MEM_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_DDRPHYCFG_SEL, .sel = 0 }, /* 0: clk26m */
#define PLL_PWR_ON (1 << 0) { .id = TOP_MM_SEL, .sel = 1 }, /* 1: vencpll_d2 */
#define PLL_EN (1 << 0) /* CLK_CFG_1 */
#define PLL_ISO (1 << 1) { .id = TOP_PWM_SEL, .sel = 0 }, /* 0: clk26m */
#define PLL_RSTB (1 << 24) { .id = TOP_VDEC_SEL, .sel = 1 }, /* 1: vcodecpll_ck */
#define PLL_PCW_CHG (1 << 31) { .id = TOP_VENC_SEL, .sel = 1 }, /* 1: vcodecpll_ck */
#define PLL_POSTDIV_MASK 0x7 { .id = TOP_MFG_SEL, .sel = 1 }, /* 1: mmpll_ck */
#define PCW_INTEGER_BITS 7 /* CLK_CFG_2 */
{ .id = TOP_CAMTG_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_SPI_SEL, .sel = 1 }, /* 1: syspll3_d2 */
{ .id = TOP_USB20_SEL, .sel = 1 }, /* 1: univpll1_d8 */
/* CLK_CFG_4 */
{ .id = TOP_MSDC30_2_SEL, .sel = 2 }, /* 2: msdcpll_d4 */
{ .id = TOP_MSDC30_3_SEL, .sel = 5 }, /* 5: msdcpll_d4 */
{ .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: syspll1_d4 */
/* CLK_CFG_5 */
{ .id = TOP_PMICSPI_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_SCP_SEL, .sel = 1 }, /* 1: syspll1_d2 */
{ .id = TOP_ATB_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_VENC_LT_SEL, .sel = 6 }, /* 6: univpll1_d2 */
/* CLK_CFG_6 */
{ .id = TOP_DPI0_SEL, .sel = 1 }, /* 1: tvdpll_d2 */
{ .id = TOP_IRDA_SEL, .sel = 1 }, /* 1: univpll2_d4 */
{ .id = TOP_CCI400_SEL, .sel = 5 }, /* 5: syspll_d2 */
{ .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */
/* CLK_CFG_7 */
{ .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */
{ .id = TOP_MEM_MFG_IN_SEL, .sel = 1 }, /* 1: mmpll_ck */
{ .id = TOP_AXI_MFG_IN_SEL, .sel = 1 }, /* 1: hd_faxi_ck */
{ .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: syspll3_d2 */
/* CLK_CFG_12 */
{ .id = TOP_SPINFI_IFR_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_HDMI_SEL, .sel = 1 }, /* 1: AD_HDMITX_CLK */
{ .id = TOP_DPILVDS_SEL, .sel = 1 }, /* 1: AD_LVDSPLL_CK */
/* CLK_CFG_13 */
{ .id = TOP_MSDC50_2_H_SEL, .sel = 2 }, /* 2: syspll2_d2 */
{ .id = TOP_HDCP_SEL, .sel = 2 }, /* 2: syspll3_d4 */
{ .id = TOP_HDCP_24M_SEL, .sel = 2 }, /* 2: univpll_d52 */
{ .id = TOP_RTC_SEL, .sel = 1 }, /* 1: clkrtc_ext */
/* CLK_CFG_3 */
{ .id = TOP_USB30_SEL, .sel = 1 }, /* 1: univpll3_d2 */
{ .id = TOP_MSDC50_0_H_SEL, .sel = 2 }, /* 2: syspll2_d2 */
{ .id = TOP_MSDC50_0_SEL, .sel = 6 }, /* 6: msdcpll_d4 */
{ .id = TOP_MSDC30_1_SEL, .sel = 2 }, /* 2: msdcpll_d4 */
};
enum pll_id { enum pll_id {
APMIXED_ARMCA15PLL, APMIXED_ARMCA15PLL,
@ -199,117 +228,76 @@ const u32 mmpll_div_rate[] = {
0, 0,
}; };
struct pll {
void *reg;
void *pwr_reg;
u32 rstb;
u8 pcwbits;
void *div_reg;
u8 div_shift;
void *pcw_reg;
u8 pcw_shift;
const u32 *div_rate;
};
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \
_pcw_reg, _pcw_shift, _div_rate) \
[_id] = { \
.reg = (void *)APMIXED_REG(_reg), \
.pwr_reg = (void *)APMIXED_REG(_pwr_reg), \
.rstb = _rstb, \
.pcwbits = _pcwbits, \
.div_reg = (void *)APMIXED_REG(_div_reg), \
.div_shift = _div_shift, \
.pcw_reg = (void *)APMIXED_REG(_pcw_reg), \
.pcw_shift = _pcw_shift, \
.div_rate = _div_rate, \
}
static const struct pll plls[] = { static const struct pll plls[] = {
PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0, 0, 21, PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0,
armca15pll_con1, 24, armca15pll_con1, 0, pll_div_rate), NO_RSTB_SHIFT, 21, armca15pll_con1, 24, armca15pll_con1, 0,
PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0, PLL_RSTB, 21, pll_div_rate),
armca7pll_con1, 24, armca7pll_con1, 0, pll_div_rate), PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0,
PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 21, PLL_RSTB_SHIFT, 21, armca7pll_con1, 24, armca7pll_con1, 0,
mainpll_con0, 4, mainpll_con1, 0, pll_div_rate), pll_div_rate),
PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 7, PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0,
univpll_con0, 4, univpll_con1, 14, univpll_div_rate), PLL_RSTB_SHIFT, 21, mainpll_con0, 4, mainpll_con1, 0,
PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, 0, 21, pll_div_rate),
mmpll_con1, 24, mmpll_con1, 0, mmpll_div_rate), PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0,
PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 21, PLL_RSTB_SHIFT, 7, univpll_con0, 4, univpll_con1, 14,
msdcpll_con0, 4, msdcpll_con1, 0, pll_div_rate), univpll_div_rate),
PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0, 0, 21, PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0,
vencpll_con0, 4, vencpll_con1, 0, pll_div_rate), NO_RSTB_SHIFT, 21, mmpll_con1, 24, mmpll_con1, 0,
PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 21, mmpll_div_rate),
tvdpll_con0, 4, tvdpll_con1, 0, pll_div_rate), PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0,
PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, 0, 21, NO_RSTB_SHIFT, 21, msdcpll_con0, 4, msdcpll_con1, 0,
mpll_con0, 4, mpll_con1, 0, pll_div_rate), pll_div_rate),
PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0, 0, 21, PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0,
vcodecpll_con0, 4, vcodecpll_con1, 0, pll_div_rate), NO_RSTB_SHIFT, 21, vencpll_con0, 4, vencpll_con1, 0,
PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, 0, 31, pll_div_rate),
apll1_con0, 4, apll1_con1, 0, pll_div_rate), PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0,
PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, 0, 31, NO_RSTB_SHIFT, 21, tvdpll_con0, 4, tvdpll_con1, 0,
apll2_con0, 4, apll2_con1, 0, pll_div_rate), pll_div_rate),
PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0, 0, 21, PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0,
lvdspll_con0, 4, lvdspll_con1, 0, pll_div_rate), NO_RSTB_SHIFT, 21, mpll_con0, 4, mpll_con1, 0,
PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0, 0, 21, pll_div_rate),
msdcpll2_con0, 4, msdcpll2_con1, 0, pll_div_rate), PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0,
NO_RSTB_SHIFT, 21, vcodecpll_con0, 4, vcodecpll_con1, 0,
pll_div_rate),
PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0,
NO_RSTB_SHIFT, 31, apll1_con0, 4, apll1_con1, 0,
pll_div_rate),
PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0,
NO_RSTB_SHIFT, 31, apll2_con0, 4, apll2_con1, 0,
pll_div_rate),
PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0,
NO_RSTB_SHIFT, 21, lvdspll_con0, 4, lvdspll_con1, 0,
pll_div_rate),
PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0,
NO_RSTB_SHIFT, 21, msdcpll2_con0, 4, msdcpll2_con1, 0,
pll_div_rate),
}; };
static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv) struct rate {
enum pll_id id;
u32 rate;
};
static const struct rate rates[] = {
{ .id = APMIXED_ARMCA15PLL, .rate = ARMCA15PLL_HZ },
{ .id = APMIXED_ARMCA7PLL, .rate = ARMCA7PLL_HZ },
{ .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
{ .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
{ .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
{ .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
{ .id = APMIXED_VENCPLL, .rate = VENCPLL_HZ },
{ .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
{ .id = APMIXED_MPLL, .rate = MPLL_HZ },
{ .id = APMIXED_VCODECPLL, .rate = VCODECPLL_HZ },
{ .id = APMIXED_LVDSPLL, .rate = LVDSPLL_HZ },
{ .id = APMIXED_MSDCPLL2, .rate = MSDCPLL2_HZ },
{ .id = APMIXED_APLL1, .rate = APLL1_HZ },
{ .id = APMIXED_APLL2, .rate = APLL2_HZ },
};
void pll_set_pcw_change(const struct pll *pll)
{ {
u32 val; setbits_le32(pll->pcw_reg, PLL_PCW_CHG);
/* set postdiv */
val = read32(pll->div_reg);
val &= ~(PLL_POSTDIV_MASK << pll->div_shift);
val |= postdiv << pll->div_shift;
/* postdiv and pcw need to set at the same time if on same register */
if (pll->div_reg != pll->pcw_reg) {
write32(pll->div_reg, val);
val = read32(pll->pcw_reg);
}
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
val |= PLL_PCW_CHG;
write32(pll->pcw_reg, val);
}
static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,
u32 freq)
{
const u32 fin_hz = CLK26M_HZ;
const u32 *div_rate = pll->div_rate;
u32 val;
assert(freq <= div_rate[0]);
assert(freq >= 1 * GHz / 16);
for (val = 1; div_rate[val] != 0; val++) {
if (freq > div_rate[val])
break;
}
val--;
*postdiv = val;
/* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */
val += pll->pcwbits - PCW_INTEGER_BITS;
*pcw = ((u64)freq << val) / fin_hz;
}
static int pll_set_rate(const struct pll *pll, u32 rate)
{
u32 pcw = 0;
u32 postdiv;
pll_calc_values(pll, &pcw, &postdiv, rate);
pll_set_rate_regs(pll, pcw, postdiv);
return 0;
} }
void mt_pll_init(void) void mt_pll_init(void)
@ -317,10 +305,10 @@ void mt_pll_init(void)
int i; int i;
/* reduce CLKSQ disable time */ /* reduce CLKSQ disable time */
write32(&mt8173_apmixed->clksq_stb_con0, (0x05 << 8) | (0x01 << 0)); write32(&mtk_apmixed->clksq_stb_con0, (0x05 << 8) | (0x01 << 0));
/* extend PWR/ISO control timing to 1us */ /* extend PWR/ISO control timing to 1us */
write32(&mt8173_apmixed->pll_iso_con0, (0x8 << 16) | (0x8 << 0)); write32(&mtk_apmixed->pll_iso_con0, (0x8 << 16) | (0x8 << 0));
write32(&mt8173_apmixed->ap_pll_con6, 0x00000000); write32(&mtk_apmixed->ap_pll_con6, 0x00000000);
/************* /*************
* xPLL PWR ON * xPLL PWR ON
@ -328,7 +316,8 @@ void mt_pll_init(void)
for (i = 0; i < APMIXED_NR_PLL; i++) for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ /* wait for xPLL_PWR_ON ready (min delay is 1us) */
udelay(PLL_PWR_ON_DELAY);
/****************** /******************
* xPLL ISO Disable * xPLL ISO Disable
@ -339,21 +328,8 @@ void mt_pll_init(void)
/******************** /********************
* xPLL Frequency Set * xPLL Frequency Set
*********************/ *********************/
for (i = 0; i < ARRAY_SIZE(rates); i++)
pll_set_rate(&plls[APMIXED_ARMCA15PLL], ARMCA15PLL_HZ); pll_set_rate(&plls[rates[i].id], rates[i].rate);
pll_set_rate(&plls[APMIXED_ARMCA7PLL], ARMCA7PLL_HZ);
pll_set_rate(&plls[APMIXED_MAINPLL], MAINPLL_HZ);
pll_set_rate(&plls[APMIXED_UNIVPLL], UNIVPLL_HZ);
pll_set_rate(&plls[APMIXED_MMPLL], MMPLL_HZ);
pll_set_rate(&plls[APMIXED_MSDCPLL], MSDCPLL_HZ);
pll_set_rate(&plls[APMIXED_VENCPLL], VENCPLL_HZ);
pll_set_rate(&plls[APMIXED_TVDPLL], TVDPLL_HZ);
pll_set_rate(&plls[APMIXED_MPLL], MPLL_HZ);
pll_set_rate(&plls[APMIXED_VCODECPLL], VCODECPLL_HZ);
pll_set_rate(&plls[APMIXED_LVDSPLL], LVDSPLL_HZ);
pll_set_rate(&plls[APMIXED_MSDCPLL2], MSDCPLL2_HZ);
pll_set_rate(&plls[APMIXED_APLL1], APLL1_HZ);
pll_set_rate(&plls[APMIXED_APLL2], APLL2_HZ);
/*********************** /***********************
* xPLL Frequency Enable * xPLL Frequency Enable
@ -361,14 +337,14 @@ void mt_pll_init(void)
for (i = 0; i < APMIXED_NR_PLL; i++) for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].reg, PLL_EN); setbits_le32(plls[i].reg, PLL_EN);
udelay(40); /* wait for PLL stable (min delay is 20us) */ udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */
/*************** /***************
* xPLL DIV RSTB * xPLL DIV RSTB
****************/ ****************/
for (i = 0; i < APMIXED_NR_PLL; i++) { for (i = 0; i < APMIXED_NR_PLL; i++) {
if (plls[i].rstb) if (plls[i].rstb_shift != NO_RSTB_SHIFT)
setbits_le32(plls[i].reg, plls[i].rstb); setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
} }
/************** /**************
@ -378,68 +354,20 @@ void mt_pll_init(void)
/* enable infrasys DCM */ /* enable infrasys DCM */
setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1); setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1);
write32(&mt8173_topckgen->clk_mode, 0x1); write32(&mtk_topckgen->clk_mode, 0x1);
write32(&mt8173_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */ write32(&mtk_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */
/************ /************
* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
*************/ *************/
for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
/* CLK_CFG_0 */ mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
mux_set_sel(&muxes[TOP_AXI_SEL], 5); /* 5: univpll2_d2 */
mux_set_sel(&muxes[TOP_MEM_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_DDRPHYCFG_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_MM_SEL], 1); /* 1: vencpll_d2 */
/* CLK_CFG_1 */
mux_set_sel(&muxes[TOP_PWM_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_VDEC_SEL], 1); /* 1: vcodecpll_ck */
mux_set_sel(&muxes[TOP_VENC_SEL], 1); /* 1: vcodecpll_ck */
mux_set_sel(&muxes[TOP_MFG_SEL], 1); /* 1: mmpll_ck */
/* CLK_CFG_2 */
mux_set_sel(&muxes[TOP_CAMTG_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_UART_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_SPI_SEL], 1); /* 1: syspll3_d2 */
mux_set_sel(&muxes[TOP_USB20_SEL], 1); /* 1: univpll1_d8 */
/* CLK_CFG_4 */
mux_set_sel(&muxes[TOP_MSDC30_2_SEL], 2); /* 2: msdcpll_d4 */
mux_set_sel(&muxes[TOP_MSDC30_3_SEL], 5); /* 5: msdcpll_d4 */
mux_set_sel(&muxes[TOP_AUDIO_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_AUD_INTBUS_SEL], 1); /* 1: syspll1_d4 */
/* CLK_CFG_5 */
mux_set_sel(&muxes[TOP_PMICSPI_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_SCP_SEL], 1); /* 1: syspll1_d2 */
mux_set_sel(&muxes[TOP_ATB_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_VENC_LT_SEL], 6); /* 6: univpll1_d2 */
/* CLK_CFG_6 */
mux_set_sel(&muxes[TOP_DPI0_SEL], 1); /* 1: tvdpll_d2 */
mux_set_sel(&muxes[TOP_IRDA_SEL], 1); /* 1: univpll2_d4 */
mux_set_sel(&muxes[TOP_CCI400_SEL], 5); /* 5: syspll_d2 */
mux_set_sel(&muxes[TOP_AUD_1_SEL], 1); /* 1: apll1_ck */
/* CLK_CFG_7 */
mux_set_sel(&muxes[TOP_AUD_2_SEL], 1); /* 1: apll2_ck */
mux_set_sel(&muxes[TOP_MEM_MFG_IN_SEL], 1); /* 1: mmpll_ck */
mux_set_sel(&muxes[TOP_AXI_MFG_IN_SEL], 1); /* 1: hd_faxi_ck */
mux_set_sel(&muxes[TOP_SCAM_SEL], 1); /* 1: syspll3_d2 */
/* CLK_CFG_12 */
mux_set_sel(&muxes[TOP_SPINFI_IFR_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_HDMI_SEL], 1); /* 1: AD_HDMITX_CLK */
mux_set_sel(&muxes[TOP_DPILVDS_SEL], 1); /* 1: AD_LVDSPLL_CK */
/* CLK_CFG_13 */
mux_set_sel(&muxes[TOP_MSDC50_2_H_SEL], 2); /* 2: syspll2_d2 */
mux_set_sel(&muxes[TOP_HDCP_SEL], 2); /* 2: syspll3_d4 */
mux_set_sel(&muxes[TOP_HDCP_24M_SEL], 2); /* 2: univpll_d52 */
mux_set_sel(&muxes[TOP_RTC_SEL], 1); /* 1: clkrtc_ext */
/* CLK_CFG_3 */
mux_set_sel(&muxes[TOP_USB30_SEL], 1); /* 1: univpll3_d2 */
mux_set_sel(&muxes[TOP_MSDC50_0_H_SEL], 2); /* 2: syspll2_d2 */
mux_set_sel(&muxes[TOP_MSDC50_0_SEL], 6); /* 6: msdcpll_d4 */
mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 2); /* 2: msdcpll_d4 */
/* enable scpsys clock off control */ /* enable scpsys clock off control */
write32(&mt8173_topckgen->clk_scp_cfg_0, write32(&mtk_topckgen->clk_scp_cfg_0,
(1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) | (1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) |
(1 << 1) | (1 << 0)); (1 << 1) | (1 << 0));
write32(&mt8173_topckgen->clk_scp_cfg_1, write32(&mtk_topckgen->clk_scp_cfg_1,
(1 << 4) | (1 << 2) | (1 << 0)); (1 << 4) | (1 << 2) | (1 << 0));
} }
@ -447,16 +375,16 @@ void mt_pll_init(void)
void mt_pll_enable_ssusb_clk(void) void mt_pll_enable_ssusb_clk(void)
{ {
/* set RG_LTECLKSQ_EN */ /* set RG_LTECLKSQ_EN */
setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1); setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1);
udelay(100); /* wait for PLL stable */ udelay(100); /* wait for PLL stable */
/* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */
setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1); setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1 << 1);
setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1); setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1);
udelay(100); /* wait for PLL stable */ udelay(100); /* wait for PLL stable */
/* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */
setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); setbits_le32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));
} }
@ -487,19 +415,19 @@ void mt_pll_set_aud_div(u32 rate)
if (apll1) { if (apll1) {
/* mclk */ /* mclk */
clrbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5); clrbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_1, 0xff << 8, clrsetbits_le32(&mtk_topckgen->clk_auddiv_1, 0xff << 8,
mclk_div << 8); mclk_div << 8);
/* bclk */ /* bclk */
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 24, clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 24,
7 << 24); 7 << 24);
} else { } else {
/* mclk */ /* mclk */
setbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5); setbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_2, 0xff << 8, clrsetbits_le32(&mtk_topckgen->clk_auddiv_2, 0xff << 8,
mclk_div << 8); mclk_div << 8);
/* bclk */ /* bclk */
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 28, clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 28,
7 << 28); 7 << 28);
} }
} }
@ -513,19 +441,19 @@ void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params)
u32 mpll_sdm_pcw_20_0 = 0xF13B1; u32 mpll_sdm_pcw_20_0 = 0xF13B1;
/* disable MPLL for adjusting memory clk frequency */ /* disable MPLL for adjusting memory clk frequency */
clrbits_le32(&mt8173_apmixed->mpll_con0, BIT(0)); clrbits_le32(&mtk_apmixed->mpll_con0, BIT(0));
/* MPLL configuration: mode selection */ /* MPLL configuration: mode selection */
setbits_le32(&mt8173_apmixed->mpll_con0, BIT(16)); setbits_le32(&mtk_apmixed->mpll_con0, BIT(16));
clrbits_le32(&mt8173_apmixed->mpll_con0, 0x7 << 4); clrbits_le32(&mtk_apmixed->mpll_con0, 0x7 << 4);
clrbits_le32(&mt8173_apmixed->pll_test_con0, 1 << 31); clrbits_le32(&mtk_apmixed->pll_test_con0, 1 << 31);
/* set RG_MPLL_SDM_PCW for feedback divide ratio */ /* set RG_MPLL_SDM_PCW for feedback divide ratio */
clrsetbits_le32(&mt8173_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); clrsetbits_le32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0);
} }
void mt_mem_pll_config_post(void) void mt_mem_pll_config_post(void)
{ {
/* power up sequence starts: enable MPLL */ /* power up sequence starts: enable MPLL */
setbits_le32(&mt8173_apmixed->mpll_con0, BIT(0)); setbits_le32(&mtk_apmixed->mpll_con0, BIT(0));
} }
void mt_mem_pll_mux(void) void mt_mem_pll_mux(void)