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soc/intel/xeon_sp/*/Kconfig: Refactor out and remove SOC_SPECIFIC_OPTIONS 

Move specific selections to {cpx,skx,spr} and remove
dummy SOC_SPECIFIC_OPTIONS

Change-Id: I71e41deb0478bf4d04395c88fc7b68df1ea83ac0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Elyes Haouas 2023-08-04 07:42:33 +02:00
parent 77c226ac9b
commit 171ad51b42
4 changed files with 31 additions and 40 deletions
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34
src/soc/intel/xeon_sp/Kconfig
View File

@ -4,38 +4,6 @@ source "src/soc/intel/xeon_sp/*/Kconfig"
config XEON_SP_COMMON_BASE
bool
config SOC_INTEL_SKYLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_0
select NO_FSP_TEMP_RAM_EXIT
help
Intel Skylake-SP support
config SOC_INTEL_COOPERLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_2
select CACHE_MRC_SETTINGS
select NO_FSP_TEMP_RAM_EXIT
help
Intel Cooper Lake-SP support
config SOC_INTEL_SAPPHIRERAPIDS_SP
bool
select CACHE_MRC_SETTINGS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select PLATFORM_USES_FSP2_3
select SOC_INTEL_CSE_SERVER_SKU
select XEON_SP_COMMON_BASE
help
Intel Sapphire Rapids-SP support
if XEON_SP_COMMON_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
@ -72,6 +40,8 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
if XEON_SP_COMMON_BASE
config MAINBOARD_USES_FSP2_0
bool
default y

14
src/soc/intel/xeon_sp/cpx/Kconfig
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@ -1,10 +1,16 @@
## SPDX-License-Identifier: GPL-2.0-only
if SOC_INTEL_COOPERLAKE_SP
config SOC_SPECIFIC_OPTIONS
def_bool y
config SOC_INTEL_COOPERLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_2
select CACHE_MRC_SETTINGS
select NO_FSP_TEMP_RAM_EXIT
select HAVE_INTEL_FSP_REPO
help
Intel Cooper Lake-SP support
if SOC_INTEL_COOPERLAKE_SP
config FSP_HEADER_PATH
default "3rdparty/fsp/CedarIslandFspBinPkg/Include"

8
src/soc/intel/xeon_sp/skx/Kconfig
View File

@ -1,5 +1,13 @@
## SPDX-License-Identifier: GPL-2.0-only
config SOC_INTEL_SKYLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_0
select NO_FSP_TEMP_RAM_EXIT
help
Intel Skylake-SP support
if SOC_INTEL_SKYLAKE_SP
config MAINBOARD_USES_FSP2_0

15
src/soc/intel/xeon_sp/spr/Kconfig
View File

@ -1,14 +1,21 @@
## SPDX-License-Identifier: GPL-2.0-only
if SOC_INTEL_SAPPHIRERAPIDS_SP
config SOC_SPECIFIC_OPTIONS
def_bool y
config SOC_INTEL_SAPPHIRERAPIDS_SP
bool
select MICROCODE_BLOB_NOT_HOOKED_UP
select SAVE_MRC_AFTER_FSPS
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select DISABLE_ACPI_HIBERNATE
select DEFAULT_X2APIC_RUNTIME
select CACHE_MRC_SETTINGS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select PLATFORM_USES_FSP2_3
select SOC_INTEL_CSE_SERVER_SKU
select XEON_SP_COMMON_BASE
help
Intel Sapphire Rapids-SP support
if SOC_INTEL_SAPPHIRERAPIDS_SP
config CHIPSET_DEVICETREE
string