mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus
Initial copy of olivehillplus. Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15917 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Fabian Kunkel
Kyösti Mälkki
parent
b0f81518b5
commit
171e2c965a
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include <northbridge/amd/pi/BiosCallOuts.h>
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#include "Ids.h"
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#include "heapManager.h"
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#include "FchPlatform.h"
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#include "cbfs.h"
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#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
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#include "imc.h"
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#endif
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#include "hudson.h"
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/**
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* Realtek ALC272 CODEC Verb Table
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*/
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static const CODEC_ENTRY Alc272_VerbTbl[] = {
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{0x11, 0x411111F0}, // - SPDIF_OUT2
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{0x12, 0x411111F0}, // - DMIC_1/2
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{0x13, 0x411111F0}, // - DMIC_3/4
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{0x14, 0x411111F0}, // Port D - LOUT1
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{0x15, 0x411111F0}, // Port A - LOUT2
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{0x16, 0x411111F0}, //
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{0x17, 0x411111F0}, // Port H - MONO
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{0x18, 0x01a19840}, // Port B - MIC1
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{0x19, 0x411111F0}, // Port F - MIC2
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{0x1a, 0x01813030}, // Port C - LINE1
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{0x1b, 0x411111F0}, // Port E - LINE2
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{0x1d, 0x40251E05}, // - PCBEEP
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{0x1e, 0x01441120}, // - SPDIF_OUT1
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{0x21, 0x01214010}, // Port I - HPOUT
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{0xff, 0xffffffff}
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};
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static const CODEC_TBL_LIST CodecTableList[] =
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{
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{0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
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{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
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};
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#define FAN_INPUT_INTERNAL_DIODE 0
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#define FAN_INPUT_TEMP0 1
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#define FAN_INPUT_TEMP1 2
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#define FAN_INPUT_TEMP2 3
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#define FAN_INPUT_TEMP3 4
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#define FAN_INPUT_TEMP0_FILTER 5
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#define FAN_INPUT_ZERO 6
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#define FAN_INPUT_DISABLED 7
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#define FAN_AUTOMODE (1 << 0)
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#define FAN_LINEARMODE (1 << 1)
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#define FAN_STEPMODE ~(1 << 1)
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#define FAN_POLARITY_HIGH (1 << 2)
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#define FAN_POLARITY_LOW ~(1 << 2)
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/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
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#define FREQ_28KHZ 0x0
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#define FREQ_25KHZ 0x1
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#define FREQ_23KHZ 0x2
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#define FREQ_21KHZ 0x3
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#define FREQ_29KHZ 0x4
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#define FREQ_18KHZ 0x5
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#define FREQ_100HZ 0xF7
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#define FREQ_87HZ 0xF8
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#define FREQ_58HZ 0xF9
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#define FREQ_44HZ 0xFA
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#define FREQ_35HZ 0xFB
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#define FREQ_29HZ 0xFC
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#define FREQ_22HZ 0xFD
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#define FREQ_14HZ 0xFE
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#define FREQ_11HZ 0xFF
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/*
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* Hardware Monitor Fan Control
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* Hardware limitation:
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* HWM will fail to read the input temperature via I2C if other
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* software switches the I2C address. AMD recommends using IMC
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* to control fans, instead of HWM.
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*/
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static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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{
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FCH_HWM_FAN_CTR oem_factl[5] = {
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/*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
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/* DB-FT3 FanOUT0 Fan header J32 */
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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/* DB-FT3 FanOUT1 Fan header J31*/
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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};
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LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
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/* Enable IMC fan control. the recommended way */
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#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
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/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
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FchParams->Hwm.HwMonitorEnable = TRUE;
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FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */
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FchParams->Imc.ImcEnable = TRUE;
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FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
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FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
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LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
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/* Thermal Zone Parameter */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
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/* IMC Fan Policy temperature thresholds */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
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/* IMC Fan Policy PWM Settings */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
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/* IMC Function */
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FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8;
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/* NOTE:
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* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
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* AGESA put EcDefaultMessage as global data in ROM, so we can't override it.
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* so we remove it from AGESA code. Please See FchInitLateHwm.
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*/
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#else /* HWM fan control, using the alternative method */
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FchParams->Imc.ImcEnable = FALSE;
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FchParams->Hwm.HwMonitorEnable = TRUE;
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FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */
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#endif /* CONFIG_HUDSON_IMC_FWM */
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}
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
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FchParams->FchReset.SataEnable = hudson_sata_enable();
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FchParams->FchReset.IdeEnable = hudson_ide_enable();
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FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams->FchReset.Xhci1Enable = FALSE;
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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oem_fan_control(FchParams);
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/* XHCI configuration */
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FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams->Usb.Xhci1Enable = FALSE;
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/* sata configuration */
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FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
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switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams->Sata.SataIdeMode = TRUE;
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break;
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}
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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@ -0,0 +1,54 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
if BOARD_ODE_E21XX
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_PI_00730F01
|
||||
select NORTHBRIDGE_AMD_PI_00730F01
|
||||
select SOUTHBRIDGE_AMD_PI_AVALON
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_MP_TABLE
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select GFXUMA
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default bap/ode_e21XX
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ODE_E21XX"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 11
|
||||
|
||||
config ONBOARD_VGA_IS_PRIMARY
|
||||
bool
|
||||
default y
|
||||
|
||||
config HUDSON_LEGACY_FREE
|
||||
bool
|
||||
default y
|
||||
|
||||
endif # BOARD_ODE_E21XX
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
config BOARD_ODE_E21XX
|
||||
bool "ODE_e21xx"
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += BiosCallOuts.c
|
||||
romstage-y += OemCustomize.c
|
||||
|
||||
ramstage-y += BiosCallOuts.c
|
||||
ramstage-y += OemCustomize.c
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <northbridge/amd/pi/agesawrapper.h>
|
||||
|
||||
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
|
||||
|
||||
static const PCIe_PORT_DESCRIPTOR PortList [] = {
|
||||
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x01, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x02, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x03, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x04, 0)
|
||||
},
|
||||
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
|
||||
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
|
||||
HotplugDisabled,
|
||||
PcieGenMaxSupported,
|
||||
PcieGenMaxSupported,
|
||||
AspmDisabled, 0x05, 0)
|
||||
}
|
||||
};
|
||||
|
||||
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
|
||||
/* DP0 to HDMI0/DP */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to FCH */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to HDMI1/DP */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
|
||||
},
|
||||
};
|
||||
|
||||
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
|
||||
.Flags = DESCRIPTOR_TERMINATE_LIST,
|
||||
.SocketId = 0,
|
||||
.PciePortList = PortList,
|
||||
.DdiLinkList = DdiList
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* OemCustomizeInitEarly
|
||||
*
|
||||
* Description:
|
||||
* This stub function will call the host environment through the binary block
|
||||
* interface (call-out port) to provide a user hook opportunity
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] *InitEarly
|
||||
*
|
||||
* @retval VOID
|
||||
*
|
||||
**/
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
VOID
|
||||
OemCustomizeInitEarly (
|
||||
IN OUT AMD_EARLY_PARAMS *InitEarly
|
||||
)
|
||||
{
|
||||
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
|
||||
}
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
|
||||
Field(IMIO , ByteAcc, NoLock, Preserve) {
|
||||
IMCX,8,
|
||||
IMCA,8
|
||||
}
|
||||
|
||||
IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
|
||||
Offset(0x80),
|
||||
MSTI, 8,
|
||||
MITS, 8,
|
||||
MRG0, 8,
|
||||
MRG1, 8,
|
||||
MRG2, 8,
|
||||
MRG3, 8,
|
||||
}
|
||||
|
||||
Method(WACK, 0)
|
||||
{
|
||||
Store(0, Local0)
|
||||
While (LNotEqual(Local0, 0xFA)) {
|
||||
Store(MRG0, Local0)
|
||||
Sleep(10)
|
||||
}
|
||||
}
|
||||
|
||||
//Init
|
||||
Method (ITZE, 0)
|
||||
{
|
||||
Store(0, MRG0)
|
||||
Store(0xB5, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x96, MSTI)
|
||||
WACK()
|
||||
|
||||
Store(0, MRG0)
|
||||
Store(0, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x80, MSTI)
|
||||
WACK()
|
||||
|
||||
Or(MRG2, 0x01, Local0)
|
||||
|
||||
Store(0, MRG0)
|
||||
Store(0, MRG1)
|
||||
Store(Local0, MRG2)
|
||||
Store(0x81, MSTI)
|
||||
WACK()
|
||||
}
|
||||
|
||||
//Sleep
|
||||
Method (IMSP, 0)
|
||||
{
|
||||
Store(0, MRG0)
|
||||
Store(0xB5, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x96, MSTI)
|
||||
WACK()
|
||||
|
||||
Store(0, MRG0)
|
||||
Store(1, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x98, MSTI)
|
||||
WACK()
|
||||
|
||||
Store(0, MRG0)
|
||||
Store(0xB4, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x96, MSTI)
|
||||
WACK()
|
||||
}
|
||||
|
||||
//Wake
|
||||
Method (IMWK, 0)
|
||||
{
|
||||
Store(0, MRG0)
|
||||
Store(0xB5, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x96, MSTI)
|
||||
WACK()
|
||||
|
||||
Store(0, MRG0)
|
||||
Store(0, MRG1)
|
||||
Store(0, MRG2)
|
||||
Store(0x80, MSTI)
|
||||
WACK()
|
||||
|
||||
Or(MRG2, 0x01, Local0)
|
||||
|
||||
Store(0, MRG0)
|
||||
Store(0, MRG1)
|
||||
Store(Local0, MRG2)
|
||||
Store(0x81, MSTI)
|
||||
WACK()
|
||||
}
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Scope(\_GPE) { /* Start Scope GPE */
|
||||
|
||||
/* General event 3 */
|
||||
Method(_L03) {
|
||||
/* DBGO("\\_GPE\\_L00\n") */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Legacy PM event */
|
||||
Method(_L08) {
|
||||
/* DBGO("\\_GPE\\_L08\n") */
|
||||
}
|
||||
|
||||
/* Temp warning (TWarn) event */
|
||||
Method(_L09) {
|
||||
/* DBGO("\\_GPE\\_L09\n") */
|
||||
/* Notify (\_TZ.TZ00, 0x80) */
|
||||
}
|
||||
|
||||
/* USB controller PME# */
|
||||
Method(_L0B) {
|
||||
/* DBGO("\\_GPE\\_L0B\n") */
|
||||
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* ExtEvent0 SCI event */
|
||||
Method(_L10) {
|
||||
/* DBGO("\\_GPE\\_L10\n") */
|
||||
}
|
||||
|
||||
/* ExtEvent1 SCI event */
|
||||
Method(_L11) {
|
||||
/* DBGO("\\_GPE\\_L11\n") */
|
||||
}
|
||||
|
||||
/* GPIO0 or GEvent8 event */
|
||||
Method(_L18) {
|
||||
/* DBGO("\\_GPE\\_L18\n") */
|
||||
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
|
||||
/* Azalia SCI event */
|
||||
Method(_L1B) {
|
||||
/* DBGO("\\_GPE\\_L1B\n") */
|
||||
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
|
||||
}
|
||||
} /* End Scope GPE */
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
/* No license required */
|
||||
/* No IDE functionality */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Memory related values */
|
||||
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
|
||||
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
|
||||
Name(PBLN, 0x0) /* Length of BIOS area */
|
||||
|
||||
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
|
||||
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
|
||||
Name(HPBA, 0xFED00000) /* Base address of HPET table */
|
||||
|
||||
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
|
||||
|
||||
/* Some global data */
|
||||
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
Name(PMOD, One) /* Assume APIC */
|
||||
|
||||
/* AcpiGpe0Blk */
|
||||
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
|
||||
Field(GP0B, ByteAcc, NoLock, Preserve) {
|
||||
, 11,
|
||||
USBS, 1,
|
||||
}
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - F16 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
|
||||
Package(){0x0001FFFF, 0, INTB, 0 },
|
||||
Package(){0x0001FFFF, 1, INTC, 0 },
|
||||
|
||||
|
||||
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
|
||||
/* FCH devices */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, INTC, 0 },
|
||||
Package(){0x0010FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - F15 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
|
||||
Package(){0x0001FFFF, 0, 0, 44 },
|
||||
Package(){0x0001FFFF, 1, 0, 45 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridges */
|
||||
Package(){0x0002FFFF, 0, 0, 24 },
|
||||
Package(){0x0002FFFF, 1, 0, 25 },
|
||||
Package(){0x0002FFFF, 2, 0, 26 },
|
||||
Package(){0x0002FFFF, 3, 0, 27 },
|
||||
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
|
||||
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
|
||||
Package(){0x0010FFFF, 0, 0, 0x12},
|
||||
Package(){0x0010FFFF, 1, 0, 0x11},
|
||||
|
||||
/* Bus 0, Dev 17 - SATA controller */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
/* GFX */
|
||||
Name(PS4, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 24 },
|
||||
Package(){0x0000FFFF, 1, 0, 25 },
|
||||
Package(){0x0000FFFF, 2, 0, 26 },
|
||||
Package(){0x0000FFFF, 3, 0, 27 },
|
||||
})
|
||||
|
||||
/* GPP 0 */
|
||||
Name(PS5, Package(){
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 28 },
|
||||
Package(){0x0000FFFF, 1, 0, 29 },
|
||||
Package(){0x0000FFFF, 2, 0, 30 },
|
||||
Package(){0x0000FFFF, 3, 0, 31 },
|
||||
})
|
||||
|
||||
/* GPP 1 */
|
||||
Name(PS6, Package(){
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 32 },
|
||||
Package(){0x0000FFFF, 1, 0, 33 },
|
||||
Package(){0x0000FFFF, 2, 0, 34 },
|
||||
Package(){0x0000FFFF, 3, 0, 35 },
|
||||
})
|
||||
|
||||
/* GPP 2 */
|
||||
Name(PS7, Package(){
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 36 },
|
||||
Package(){0x0000FFFF, 1, 0, 37 },
|
||||
Package(){0x0000FFFF, 2, 0, 38 },
|
||||
Package(){0x0000FFFF, 3, 0, 39 },
|
||||
})
|
||||
|
||||
/* GPP 3 */
|
||||
Name(PS8, Package(){
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS8, Package(){
|
||||
Package(){0x0000FFFF, 0, 0, 40 },
|
||||
Package(){0x0000FFFF, 1, 0, 41 },
|
||||
Package(){0x0000FFFF, 2, 0, 42 },
|
||||
Package(){0x0000FFFF, 3, 0, 43 },
|
||||
})
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
Scope(\_SI) {
|
||||
Method(_SST, 1) {
|
||||
/* DBGO("\\_SI\\_SST\n") */
|
||||
/* DBGO(" New Indicator state: ") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
}
|
||||
} /* End Scope SI */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Wake status package */
|
||||
Name(WKST,Package(){Zero, Zero})
|
||||
|
||||
/*
|
||||
* \_PTS - Prepare to Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2, etc
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*
|
||||
* The _PTS control method is executed at the beginning of the sleep process
|
||||
* for S1-S5. The sleeping value is passed to the _PTS control method. This
|
||||
* control method may be executed a relatively long time before entering the
|
||||
* sleep state and the OS may abort the operation without notification to
|
||||
* the ACPI driver. This method cannot modify the configuration or power
|
||||
* state of any device in the system.
|
||||
*/
|
||||
|
||||
External(\_SB.APTS, MethodObj)
|
||||
External(\_SB.AWAK, MethodObj)
|
||||
|
||||
Method(_PTS, 1) {
|
||||
/* DBGO("\\_PTS\n") */
|
||||
/* DBGO("From S0 to S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
/* Clear wake status structure. */
|
||||
Store(0, Index(WKST,0))
|
||||
Store(0, Index(WKST,1))
|
||||
Store(7, UPWS)
|
||||
\_SB.APTS(Arg0)
|
||||
} /* End Method(\_PTS) */
|
||||
|
||||
/*
|
||||
* \_BFS OEM Back From Sleep method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* -none-
|
||||
*/
|
||||
Method(\_BFS, 1) {
|
||||
/* DBGO("\\_BFS\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
}
|
||||
|
||||
/*
|
||||
* \_WAK System Wake method
|
||||
*
|
||||
* Entry:
|
||||
* Arg0=The value of the sleeping state S1=1, S2=2
|
||||
*
|
||||
* Exit:
|
||||
* Return package of 2 DWords
|
||||
* Dword 1 - Status
|
||||
* 0x00000000 wake succeeded
|
||||
* 0x00000001 Wake was signaled but failed due to lack of power
|
||||
* 0x00000002 Wake was signaled but failed due to thermal condition
|
||||
* Dword 2 - Power Supply state
|
||||
* if non-zero the effective S-state the power supply entered
|
||||
*/
|
||||
Method(\_WAK, 1) {
|
||||
/* DBGO("\\_WAK\n") */
|
||||
/* DBGO("From S") */
|
||||
/* DBGO(Arg0) */
|
||||
/* DBGO(" to S0\n") */
|
||||
|
||||
/* clear USB wake up signal */
|
||||
Store(1, USBS)
|
||||
|
||||
\_SB.AWAK(Arg0)
|
||||
|
||||
Return(WKST)
|
||||
} /* End Method(\_WAK) */
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
/* No license required */
|
||||
/* No thermal zone functionality */
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <northbridge/amd/pi/agesawrapper.h>
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam16.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB800 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
/* TODO: Remove the hardcode */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
|
||||
0xFEC20000, 24);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
Board name: DB-FT3b (Olive Hill+)
|
||||
Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm
|
||||
Category: eval
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#*****************************************************************************
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2013 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
chip northbridge/amd/pi/00730F01/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/pi/00730F01
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
|
||||
|
||||
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 0.2 off end # IOMMU
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # mPCIe slot
|
||||
device pci 2.3 on end # Realtek NIC
|
||||
device pci 2.4 on end # Edge Connector
|
||||
device pci 2.5 on end # Edge Connector
|
||||
device pci 8.0 on end # Platform Security Processor
|
||||
end #chip northbridge/amd/pi/00730F01
|
||||
|
||||
chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # EHCI #0
|
||||
device pci 13.0 on end # EHCI #1
|
||||
device pci 14.0 on # SMBus
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SMbus
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x439d
|
||||
device pci 14.7 on end # SD
|
||||
device pci 16.0 on end # EHCI #2
|
||||
end #chip southbridge/amd/pi/hudson
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
|
||||
end #domain
|
||||
end #northbridge/amd/pi/00730F01/root_complex
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* DefinitionBlock Statement */
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"AMD ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00010001 /* OEM Revision */
|
||||
)
|
||||
{ /* Start of ASL file */
|
||||
/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
|
||||
|
||||
/* Globals for the platform */
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
/* Describe the USB Overcurrent pins */
|
||||
#include "acpi/usb_oc.asl"
|
||||
|
||||
/* PCI IRQ mapping for the Southbridge */
|
||||
#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
|
||||
|
||||
/* Describe the processor tree (\_PR) */
|
||||
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
|
||||
|
||||
/* Contains the supported sleep states for this chipset */
|
||||
#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
|
||||
|
||||
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
|
||||
#include "acpi/sleep.asl"
|
||||
|
||||
/* System Bus */
|
||||
Scope(\_SB) { /* Start \_SB scope */
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
|
||||
#include "acpi/routing.asl"
|
||||
|
||||
Device(PWRB) {
|
||||
Name(_HID, EISAID("PNP0C0C"))
|
||||
Name(_UID, 0xAA)
|
||||
Name(_PRW, Package () {3, 0x04})
|
||||
Name(_STA, 0x0B)
|
||||
}
|
||||
|
||||
Device(PCI0) {
|
||||
/* Describe the AMD Northbridge */
|
||||
#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
|
||||
|
||||
/* Describe the AMD Fusion Controller Hub Southbridge */
|
||||
#include <southbridge/amd/pi/hudson/acpi/fch.asl>
|
||||
}
|
||||
|
||||
/* Describe PCI INT[A-H] for the Southbridge */
|
||||
#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
|
||||
|
||||
} /* End \_SB scope */
|
||||
|
||||
/* Describe SMBUS for the Southbridge */
|
||||
#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
|
||||
|
||||
/* Define the General Purpose Events for the platform */
|
||||
#include "acpi/gpe.asl"
|
||||
|
||||
/* Define the Thermal zones and methods for the platform */
|
||||
#include "acpi/thermal.asl"
|
||||
|
||||
/* Define the System Indicators for the platform */
|
||||
#include "acpi/si.asl"
|
||||
}
|
||||
/* End of ASL file */
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam16.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <northbridge/amd/pi/BiosCallOuts.h>
|
||||
#include <cpu/amd/pi/s3_resume.h>
|
||||
#include <northbridge/amd/pi/agesawrapper.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
|
||||
/**********************************************
|
||||
* enable the dedicated function in mainboard.
|
||||
**********************************************/
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
if (acpi_is_wakeup_s3())
|
||||
agesawrapper_fchs3earlyrestore();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <southbridge/amd/pi/hudson/hudson.h>
|
||||
|
||||
u8 picr_data[0x54] = {
|
||||
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x03,0x04,0x05,0x07
|
||||
};
|
||||
u8 intr_data[0x54] = {
|
||||
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
}
|
||||
|
||||
static void my_smp_write_bus(struct mp_config_table *mc,
|
||||
unsigned char id, const char *bustype)
|
||||
{
|
||||
struct mpc_config_bus *mpc;
|
||||
mpc = smp_next_mpc_entry(mc);
|
||||
memset(mpc, '\0', sizeof(*mpc));
|
||||
mpc->mpc_type = MP_BUS;
|
||||
mpc->mpc_busid = id;
|
||||
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
|
||||
smp_add_mpc_entry(mc, sizeof(*mpc));
|
||||
}
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
u8 byte;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
//mptable_write_buses(mc, NULL, &bus_isa);
|
||||
my_smp_write_bus(mc, 0, "PCI ");
|
||||
my_smp_write_bus(mc, 1, "PCI ");
|
||||
bus_isa = 0x02;
|
||||
my_smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
/* PIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
|
||||
outb(byte, 0xC00);
|
||||
outb(picr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* APIC IRQ routine */
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
|
||||
|
||||
/* SMBUS */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
|
||||
/* HD Audio */
|
||||
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
|
||||
|
||||
/* USB */
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
|
||||
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe Lan*/
|
||||
PCI_INT(0x0, 0x06, 0x0, 0x13);
|
||||
|
||||
/* FCH PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* FCH PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* FCH PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/stages.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <commonlib/loglevel.h>
|
||||
#include <cpu/amd/car.h>
|
||||
#include <northbridge/amd/pi/agesawrapper.h>
|
||||
#include <northbridge/amd/pi/agesawrapper_call.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <southbridge/amd/pi/hudson/hudson.h>
|
||||
#include <cpu/amd/pi/s3_resume.h>
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
|
||||
* LpcClk[1:0]". This following register setting has been
|
||||
* replicated in every reference design since Parmer, so it is
|
||||
* believed to be required even though it is not documented in
|
||||
* the SoC BKDGs. Without this setting, there is no serial
|
||||
* output.
|
||||
*/
|
||||
outb(0xD2, 0xcd6);
|
||||
outb(0x00, 0xcd7);
|
||||
|
||||
amd_initmmio();
|
||||
|
||||
hudson_lpc_port80();
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
post_code(0x30);
|
||||
|
||||
post_code(0x31);
|
||||
console_init();
|
||||
}
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
post_code(0x34);
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Load MPB */
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
|
||||
|
||||
/*
|
||||
* This refers to LpcClkDrvSth settling time. Without this setting, processor
|
||||
* initialization is slow or incorrect, so this wait has been replicated from
|
||||
* earlier development boards.
|
||||
*/
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < 200000; i++) inb(0xCD6);
|
||||
}
|
||||
|
||||
post_code(0x37);
|
||||
AGESAWRAPPER(amdinitreset);
|
||||
|
||||
post_code(0x38);
|
||||
printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
|
||||
|
||||
post_code(0x39);
|
||||
AGESAWRAPPER(amdinitearly);
|
||||
int s3resume = acpi_is_wakeup_s3();
|
||||
if (!s3resume) {
|
||||
post_code(0x40);
|
||||
AGESAWRAPPER(amdinitpost);
|
||||
|
||||
//PspMboxBiosCmdDramInfo();
|
||||
post_code(0x41);
|
||||
AGESAWRAPPER(amdinitenv);
|
||||
/*
|
||||
If code hangs here, please check cahaltasm.S
|
||||
*/
|
||||
disable_cache_as_ram();
|
||||
} else { /* S3 detect */
|
||||
printk(BIOS_INFO, "S3 detected\n");
|
||||
|
||||
post_code(0x60);
|
||||
AGESAWRAPPER(amdinitresume);
|
||||
|
||||
AGESAWRAPPER(amds3laterestore);
|
||||
|
||||
post_code(0x61);
|
||||
prepare_for_resume();
|
||||
}
|
||||
|
||||
outb(0xEA, 0xCD6);
|
||||
outb(0x1, 0xcd7);
|
||||
|
||||
post_code(0x50);
|
||||
copy_and_run();
|
||||
|
||||
post_code(0x54); /* Should never see this post code. */
|
||||
}
|
||||
Loading…
Reference in New Issue