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The point of the patch is to make it easier to understand the raminit 

code, specifically the difference between pre_f and f code.

The only functional changes are in printk statements.  The rest is white space.

1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks.  All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code

There is much more that could be done, but it's a start.

Abuild tested and boot tested on s2892 and serengeti_cheetah.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-06-04 20:18:42 +00:00
parent d11bd003c6
commit 1725703a1d
11 changed files with 418 additions and 502 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/dbm690t/cache_as_ram_auto.c
View File

@ -86,7 +86,7 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"

2
src/mainboard/amd/pistachio/cache_as_ram_auto.c
View File

@ -80,7 +80,7 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"

2
src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
View File

@ -124,7 +124,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "sdram/generic_sdram.c"

2
src/mainboard/technexion/tim8690/cache_as_ram_auto.c
View File

@ -86,7 +86,7 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"

14
src/northbridge/amd/amdk8/Config.lb
View File

@ -1,6 +1,7 @@
uses AGP_APERTURE_SIZE
uses HAVE_ACPI_TABLES
uses HAVE_HIGH_TABLES
uses K8_REV_F_SUPPORT
default AGP_APERTURE_SIZE=0x4000000
default HAVE_HIGH_TABLES=1
@ -10,12 +11,25 @@ config chip.h
driver northbridge.o
driver misc_control.o
if K8_REV_F_SUPPORT
makerule raminit_test
depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"
depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c"
action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
end
else
makerule raminit_test
depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"
depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c"
action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
end
end
if HAVE_ACPI_TABLES
object amdk8_acpi.o
end

263
src/northbridge/amd/amdk8/amdk8.h
View File

@ -4,269 +4,8 @@
#if K8_REV_F_SUPPORT == 1
#include "amdk8_f.h"
#else
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
#define HTTC_DIS_RD_B_P (1 << 0)
#define HTTC_DIS_RD_DW_P (1 << 1)
#define HTTC_DIS_WR_B_P (1 << 2)
#define HTTC_DIS_WR_DW_P (1 << 3)
#define HTTC_DIS_MTS (1 << 4)
#define HTTC_CPU1_EN (1 << 5)
#define HTTC_CPU_REQ_PASS_PW (1 << 6)
#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
#define HTTC_DIS_P_MEM_C (1 << 8)
#define HTTC_DIS_RMT_MEM_C (1 << 9)
#define HTTC_DIS_FILL_P (1 << 10)
#define HTTC_RSP_PASS_PW (1 << 11)
#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
#define HTTC_BUF_REL_PRI_SHIFT 13
#define HTTC_BUF_REL_PRI_MASK 3
#define HTTC_BUF_REL_PRI_64 0
#define HTTC_BUF_REL_PRI_16 1
#define HTTC_BUF_REL_PRI_8 2
#define HTTC_BUF_REL_PRI_2 3
#define HTTC_LIMIT_CLDT_CFG (1 << 15)
#define HTTC_LINT_EN (1 << 16)
#define HTTC_APIC_EXT_BRD_CST (1 << 17)
#define HTTC_APIC_EXT_ID (1 << 18)
#define HTTC_APIC_EXT_SPUR (1 << 19)
#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
#define HTTC_DS_NP_REQ_LIMIT_MASK 3
#define HTTC_DS_NP_REQ_LIMIT_NONE 0
#define HTTC_DS_NP_REQ_LIMIT_1 1
#define HTTC_DS_NP_REQ_LIMIT_4 2
#define HTTC_DS_NP_REQ_LIMIT_8 3
#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
#define HTTC_MED_PRI_BYP_CNT_MASK 3
#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
#define HTTC_HI_PRI_BYP_CNT_MASK 3
/* Function 1 */
#define PCI_IO_BASE0 0xc0
#define PCI_IO_BASE1 0xc8
#define PCI_IO_BASE2 0xd0
#define PCI_IO_BASE3 0xd8
#define PCI_IO_BASE_VGA_EN (1 << 4)
#define PCI_IO_BASE_NO_ISA (1 << 5)
/* Function 2 */
#define DRAM_CSBASE 0x40
#define DRAM_CSMASK 0x60
#define DRAM_BANK_ADDR_MAP 0x80
#define DRAM_TIMING_LOW 0x88
#define DTL_TCL_SHIFT 0
#define DTL_TCL_MASK 0x7
#define DTL_CL_2 1
#define DTL_CL_3 2
#define DTL_CL_2_5 5
#define DTL_TRC_SHIFT 4
#define DTL_TRC_MASK 0xf
#define DTL_TRC_BASE 7
#define DTL_TRC_MIN 7
#define DTL_TRC_MAX 22
#define DTL_TRFC_SHIFT 8
#define DTL_TRFC_MASK 0xf
#define DTL_TRFC_BASE 9
#define DTL_TRFC_MIN 9
#define DTL_TRFC_MAX 24
#define DTL_TRCD_SHIFT 12
#define DTL_TRCD_MASK 0x7
#define DTL_TRCD_BASE 0
#define DTL_TRCD_MIN 2
#define DTL_TRCD_MAX 6
#define DTL_TRRD_SHIFT 16
#define DTL_TRRD_MASK 0x7
#define DTL_TRRD_BASE 0
#define DTL_TRRD_MIN 2
#define DTL_TRRD_MAX 4
#define DTL_TRAS_SHIFT 20
#define DTL_TRAS_MASK 0xf
#define DTL_TRAS_BASE 0
#define DTL_TRAS_MIN 5
#define DTL_TRAS_MAX 15
#define DTL_TRP_SHIFT 24
#define DTL_TRP_MASK 0x7
#define DTL_TRP_BASE 0
#define DTL_TRP_MIN 2
#define DTL_TRP_MAX 6
#define DTL_TWR_SHIFT 28
#define DTL_TWR_MASK 0x1
#define DTL_TWR_BASE 2
#define DTL_TWR_MIN 2
#define DTL_TWR_MAX 3
#define DRAM_TIMING_HIGH 0x8c
#define DTH_TWTR_SHIFT 0
#define DTH_TWTR_MASK 0x1
#define DTH_TWTR_BASE 1
#define DTH_TWTR_MIN 1
#define DTH_TWTR_MAX 2
#define DTH_TRWT_SHIFT 4
#define DTH_TRWT_MASK 0x7
#define DTH_TRWT_BASE 1
#define DTH_TRWT_MIN 1
#define DTH_TRWT_MAX 6
#define DTH_TREF_SHIFT 8
#define DTH_TREF_MASK 0x1f
#define DTH_TREF_100MHZ_4K 0x00
#define DTH_TREF_133MHZ_4K 0x01
#define DTH_TREF_166MHZ_4K 0x02
#define DTH_TREF_200MHZ_4K 0x03
#define DTH_TREF_100MHZ_8K 0x08
#define DTH_TREF_133MHZ_8K 0x09
#define DTH_TREF_166MHZ_8K 0x0A
#define DTH_TREF_200MHZ_8K 0x0B
#define DTH_TWCL_SHIFT 20
#define DTH_TWCL_MASK 0x7
#define DTH_TWCL_BASE 1
#define DTH_TWCL_MIN 1
#define DTH_TWCL_MAX 2
#define DRAM_CONFIG_LOW 0x90
#define DCL_DLL_Disable (1<<0)
#define DCL_D_DRV (1<<1)
#define DCL_QFC_EN (1<<2)
#define DCL_DisDqsHys (1<<3)
#define DCL_Burst2Opt (1<<5)
#define DCL_DramInit (1<<8)
#define DCL_DualDIMMen (1<<9)
#define DCL_DramEnable (1<<10)
#define DCL_MemClrStatus (1<<11)
#define DCL_ESR (1<<12)
#define DCL_SRS (1<<13)
#define DCL_128BitEn (1<<16)
#define DCL_DimmEccEn (1<<17)
#define DCL_UnBufDimm (1<<18)
#define DCL_32ByteEn (1<<19)
#define DCL_x4DIMM_SHIFT 20
#define DCL_DisInRcvrs (1<<24)
#define DCL_BypMax_SHIFT 25
#define DCL_En2T (1<<28)
#define DCL_UpperCSMap (1<<29)
#define DRAM_CONFIG_HIGH 0x94
#define DCH_ASYNC_LAT_SHIFT 0
#define DCH_ASYNC_LAT_MASK 0xf
#define DCH_ASYNC_LAT_BASE 0
#define DCH_ASYNC_LAT_MIN 0
#define DCH_ASYNC_LAT_MAX 15
#define DCH_RDPREAMBLE_SHIFT 8
#define DCH_RDPREAMBLE_MASK 0xf
#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
#define DCH_IDLE_LIMIT_SHIFT 16
#define DCH_IDLE_LIMIT_MASK 0x7
#define DCH_IDLE_LIMIT_0 0
#define DCH_IDLE_LIMIT_4 1
#define DCH_IDLE_LIMIT_8 2
#define DCH_IDLE_LIMIT_16 3
#define DCH_IDLE_LIMIT_32 4
#define DCH_IDLE_LIMIT_64 5
#define DCH_IDLE_LIMIT_128 6
#define DCH_IDLE_LIMIT_256 7
#define DCH_DYN_IDLE_CTR_EN (1 << 19)
#define DCH_MEMCLK_SHIFT 20
#define DCH_MEMCLK_MASK 0x7
#define DCH_MEMCLK_100MHZ 0
#define DCH_MEMCLK_133MHZ 2
#define DCH_MEMCLK_166MHZ 5
#define DCH_MEMCLK_200MHZ 7
#define DCH_MEMCLK_VALID (1 << 25)
#define DCH_MEMCLK_EN0 (1 << 26)
#define DCH_MEMCLK_EN1 (1 << 27)
#define DCH_MEMCLK_EN2 (1 << 28)
#define DCH_MEMCLK_EN3 (1 << 29)
/* Function 3 */
#define MCA_NB_CONFIG 0x44
#define MNC_ECC_EN (1 << 22)
#define MNC_CHIPKILL_EN (1 << 23)
#define SCRUB_CONTROL 0x58
#define SCRUB_NONE 0
#define SCRUB_40ns 1
#define SCRUB_80ns 2
#define SCRUB_160ns 3
#define SCRUB_320ns 4
#define SCRUB_640ns 5
#define SCRUB_1_28us 6
#define SCRUB_2_56us 7
#define SCRUB_5_12us 8
#define SCRUB_10_2us 9
#define SCRUB_20_5us 10
#define SCRUB_41_0us 11
#define SCRUB_81_9us 12
#define SCRUB_163_8us 13
#define SCRUB_327_7us 14
#define SCRUB_655_4us 15
#define SCRUB_1_31ms 16
#define SCRUB_2_62ms 17
#define SCRUB_5_24ms 18
#define SCRUB_10_49ms 19
#define SCRUB_20_97ms 20
#define SCRUB_42ms 21
#define SCRUB_84ms 22
#define SC_DRAM_SCRUB_RATE_SHFIT 0
#define SC_DRAM_SCRUB_RATE_MASK 0x1f
#define SC_L2_SCRUB_RATE_SHIFT 8
#define SC_L2_SCRUB_RATE_MASK 0x1f
#define SC_L1D_SCRUB_RATE_SHIFT 16
#define SC_L1D_SCRUB_RATE_MASK 0x1f
#define SCRUB_ADDR_LOW 0x5C
#define SCRUB_ADDR_HIGH 0x60
#define NORTHBRIDGE_CAP 0xE8
#define NBCAP_128Bit (1 << 0)
#define NBCAP_MP (1 << 1)
#define NBCAP_BIG_MP (1 << 2)
#define NBCAP_ECC (1 << 3)
#define NBCAP_CHIPKILL_ECC (1 << 4)
#define NBCAP_MEMCLK_SHIFT 5
#define NBCAP_MEMCLK_MASK 3
#define NBCAP_MEMCLK_100MHZ 3
#define NBCAP_MEMCLK_133MHZ 2
#define NBCAP_MEMCLK_166MHZ 1
#define NBCAP_MEMCLK_200MHZ 0
#define NBCAP_MEMCTRL (1 << 8)
#define LinkConnected (1 << 0)
#define InitComplete (1 << 1)
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
#include "raminit.h"
//struct definitions
struct link_pair_st {
device_t udev;
uint32_t upos;
uint32_t uoffs;
device_t dev;
uint32_t pos;
uint32_t offs;
} __attribute__((packed));
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
struct mem_controller ctrl[NODE_NUMS];
uint32_t nodes;
struct link_pair_st link_pair[16];// enough? only in_conherent
uint32_t link_pair_num;
uint32_t ht_c_num;
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
} __attribute__((packed));
#include "amdk8_pre_f.h"
#endif
#endif /* AMDK8_H */

1
src/northbridge/amd/amdk8/amdk8_f.h
View File

@ -456,7 +456,6 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
#include "raminit.h"
//struct definitions

266
src/northbridge/amd/amdk8/amdk8_pre_f.h Normal file
View File

@ -0,0 +1,266 @@
#ifndef AMDK8_PRE_F_H
#define AMDK8_PRE_F_H
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
#define HTTC_DIS_RD_B_P (1 << 0)
#define HTTC_DIS_RD_DW_P (1 << 1)
#define HTTC_DIS_WR_B_P (1 << 2)
#define HTTC_DIS_WR_DW_P (1 << 3)
#define HTTC_DIS_MTS (1 << 4)
#define HTTC_CPU1_EN (1 << 5)
#define HTTC_CPU_REQ_PASS_PW (1 << 6)
#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
#define HTTC_DIS_P_MEM_C (1 << 8)
#define HTTC_DIS_RMT_MEM_C (1 << 9)
#define HTTC_DIS_FILL_P (1 << 10)
#define HTTC_RSP_PASS_PW (1 << 11)
#define HTTC_CHG_ISOC_TO_ORD (1 << 12)
#define HTTC_BUF_REL_PRI_SHIFT 13
#define HTTC_BUF_REL_PRI_MASK 3
#define HTTC_BUF_REL_PRI_64 0
#define HTTC_BUF_REL_PRI_16 1
#define HTTC_BUF_REL_PRI_8 2
#define HTTC_BUF_REL_PRI_2 3
#define HTTC_LIMIT_CLDT_CFG (1 << 15)
#define HTTC_LINT_EN (1 << 16)
#define HTTC_APIC_EXT_BRD_CST (1 << 17)
#define HTTC_APIC_EXT_ID (1 << 18)
#define HTTC_APIC_EXT_SPUR (1 << 19)
#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
#define HTTC_DS_NP_REQ_LIMIT_MASK 3
#define HTTC_DS_NP_REQ_LIMIT_NONE 0
#define HTTC_DS_NP_REQ_LIMIT_1 1
#define HTTC_DS_NP_REQ_LIMIT_4 2
#define HTTC_DS_NP_REQ_LIMIT_8 3
#define HTTC_MED_PRI_BYP_CNT_SHIFT 24
#define HTTC_MED_PRI_BYP_CNT_MASK 3
#define HTTC_HI_PRI_BYP_CNT_SHIFT 26
#define HTTC_HI_PRI_BYP_CNT_MASK 3
/* Function 1 */
#define PCI_IO_BASE0 0xc0
#define PCI_IO_BASE1 0xc8
#define PCI_IO_BASE2 0xd0
#define PCI_IO_BASE3 0xd8
#define PCI_IO_BASE_VGA_EN (1 << 4)
#define PCI_IO_BASE_NO_ISA (1 << 5)
/* Function 2 */
#define DRAM_CSBASE 0x40
#define DRAM_CSMASK 0x60
#define DRAM_BANK_ADDR_MAP 0x80
#define DRAM_TIMING_LOW 0x88
#define DTL_TCL_SHIFT 0
#define DTL_TCL_MASK 0x7
#define DTL_CL_2 1
#define DTL_CL_3 2
#define DTL_CL_2_5 5
#define DTL_TRC_SHIFT 4
#define DTL_TRC_MASK 0xf
#define DTL_TRC_BASE 7
#define DTL_TRC_MIN 7
#define DTL_TRC_MAX 22
#define DTL_TRFC_SHIFT 8
#define DTL_TRFC_MASK 0xf
#define DTL_TRFC_BASE 9
#define DTL_TRFC_MIN 9
#define DTL_TRFC_MAX 24
#define DTL_TRCD_SHIFT 12
#define DTL_TRCD_MASK 0x7
#define DTL_TRCD_BASE 0
#define DTL_TRCD_MIN 2
#define DTL_TRCD_MAX 6
#define DTL_TRRD_SHIFT 16
#define DTL_TRRD_MASK 0x7
#define DTL_TRRD_BASE 0
#define DTL_TRRD_MIN 2
#define DTL_TRRD_MAX 4
#define DTL_TRAS_SHIFT 20
#define DTL_TRAS_MASK 0xf
#define DTL_TRAS_BASE 0
#define DTL_TRAS_MIN 5
#define DTL_TRAS_MAX 15
#define DTL_TRP_SHIFT 24
#define DTL_TRP_MASK 0x7
#define DTL_TRP_BASE 0
#define DTL_TRP_MIN 2
#define DTL_TRP_MAX 6
#define DTL_TWR_SHIFT 28
#define DTL_TWR_MASK 0x1
#define DTL_TWR_BASE 2
#define DTL_TWR_MIN 2
#define DTL_TWR_MAX 3
#define DRAM_TIMING_HIGH 0x8c
#define DTH_TWTR_SHIFT 0
#define DTH_TWTR_MASK 0x1
#define DTH_TWTR_BASE 1
#define DTH_TWTR_MIN 1
#define DTH_TWTR_MAX 2
#define DTH_TRWT_SHIFT 4
#define DTH_TRWT_MASK 0x7
#define DTH_TRWT_BASE 1
#define DTH_TRWT_MIN 1
#define DTH_TRWT_MAX 6
#define DTH_TREF_SHIFT 8
#define DTH_TREF_MASK 0x1f
#define DTH_TREF_100MHZ_4K 0x00
#define DTH_TREF_133MHZ_4K 0x01
#define DTH_TREF_166MHZ_4K 0x02
#define DTH_TREF_200MHZ_4K 0x03
#define DTH_TREF_100MHZ_8K 0x08
#define DTH_TREF_133MHZ_8K 0x09
#define DTH_TREF_166MHZ_8K 0x0A
#define DTH_TREF_200MHZ_8K 0x0B
#define DTH_TWCL_SHIFT 20
#define DTH_TWCL_MASK 0x7
#define DTH_TWCL_BASE 1
#define DTH_TWCL_MIN 1
#define DTH_TWCL_MAX 2
#define DRAM_CONFIG_LOW 0x90
#define DCL_DLL_Disable (1<<0)
#define DCL_D_DRV (1<<1)
#define DCL_QFC_EN (1<<2)
#define DCL_DisDqsHys (1<<3)
#define DCL_Burst2Opt (1<<5)
#define DCL_DramInit (1<<8)
#define DCL_DualDIMMen (1<<9)
#define DCL_DramEnable (1<<10)
#define DCL_MemClrStatus (1<<11)
#define DCL_ESR (1<<12)
#define DCL_SRS (1<<13)
#define DCL_128BitEn (1<<16)
#define DCL_DimmEccEn (1<<17)
#define DCL_UnBuffDimm (1<<18)
#define DCL_32ByteEn (1<<19)
#define DCL_x4DIMM_SHIFT 20
#define DCL_DisInRcvrs (1<<24)
#define DCL_BypMax_SHIFT 25
#define DCL_En2T (1<<28)
#define DCL_UpperCSMap (1<<29)
#define DRAM_CONFIG_HIGH 0x94
#define DCH_ASYNC_LAT_SHIFT 0
#define DCH_ASYNC_LAT_MASK 0xf
#define DCH_ASYNC_LAT_BASE 0
#define DCH_ASYNC_LAT_MIN 0
#define DCH_ASYNC_LAT_MAX 15
#define DCH_RDPREAMBLE_SHIFT 8
#define DCH_RDPREAMBLE_MASK 0xf
#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
#define DCH_IDLE_LIMIT_SHIFT 16
#define DCH_IDLE_LIMIT_MASK 0x7
#define DCH_IDLE_LIMIT_0 0
#define DCH_IDLE_LIMIT_4 1
#define DCH_IDLE_LIMIT_8 2
#define DCH_IDLE_LIMIT_16 3
#define DCH_IDLE_LIMIT_32 4
#define DCH_IDLE_LIMIT_64 5
#define DCH_IDLE_LIMIT_128 6
#define DCH_IDLE_LIMIT_256 7
#define DCH_DYN_IDLE_CTR_EN (1 << 19)
#define DCH_MEMCLK_SHIFT 20
#define DCH_MEMCLK_MASK 0x7
#define DCH_MEMCLK_100MHZ 0
#define DCH_MEMCLK_133MHZ 2
#define DCH_MEMCLK_166MHZ 5
#define DCH_MEMCLK_200MHZ 7
#define DCH_MEMCLK_VALID (1 << 25)
#define DCH_MEMCLK_EN0 (1 << 26)
#define DCH_MEMCLK_EN1 (1 << 27)
#define DCH_MEMCLK_EN2 (1 << 28)
#define DCH_MEMCLK_EN3 (1 << 29)
/* Function 3 */
#define MCA_NB_CONFIG 0x44
#define MNC_ECC_EN (1 << 22)
#define MNC_CHIPKILL_EN (1 << 23)
#define SCRUB_CONTROL 0x58
#define SCRUB_NONE 0
#define SCRUB_40ns 1
#define SCRUB_80ns 2
#define SCRUB_160ns 3
#define SCRUB_320ns 4
#define SCRUB_640ns 5
#define SCRUB_1_28us 6
#define SCRUB_2_56us 7
#define SCRUB_5_12us 8
#define SCRUB_10_2us 9
#define SCRUB_20_5us 10
#define SCRUB_41_0us 11
#define SCRUB_81_9us 12
#define SCRUB_163_8us 13
#define SCRUB_327_7us 14
#define SCRUB_655_4us 15
#define SCRUB_1_31ms 16
#define SCRUB_2_62ms 17
#define SCRUB_5_24ms 18
#define SCRUB_10_49ms 19
#define SCRUB_20_97ms 20
#define SCRUB_42ms 21
#define SCRUB_84ms 22
#define SC_DRAM_SCRUB_RATE_SHFIT 0
#define SC_DRAM_SCRUB_RATE_MASK 0x1f
#define SC_L2_SCRUB_RATE_SHIFT 8
#define SC_L2_SCRUB_RATE_MASK 0x1f
#define SC_L1D_SCRUB_RATE_SHIFT 16
#define SC_L1D_SCRUB_RATE_MASK 0x1f
#define SCRUB_ADDR_LOW 0x5C
#define SCRUB_ADDR_HIGH 0x60
#define NORTHBRIDGE_CAP 0xE8
#define NBCAP_128Bit (1 << 0)
#define NBCAP_MP (1 << 1)
#define NBCAP_BIG_MP (1 << 2)
#define NBCAP_ECC (1 << 3)
#define NBCAP_CHIPKILL_ECC (1 << 4)
#define NBCAP_MEMCLK_SHIFT 5
#define NBCAP_MEMCLK_MASK 3
#define NBCAP_MEMCLK_100MHZ 3
#define NBCAP_MEMCLK_133MHZ 2
#define NBCAP_MEMCLK_166MHZ 1
#define NBCAP_MEMCLK_200MHZ 0
#define NBCAP_MEMCTRL (1 << 8)
#define LinkConnected (1 << 0)
#define InitComplete (1 << 1)
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
#include "raminit.h"
//struct definitions
struct link_pair_st {
device_t udev;
uint32_t upos;
uint32_t uoffs;
device_t dev;
uint32_t pos;
uint32_t offs;
} __attribute__((packed));
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
struct mem_controller ctrl[NODE_NUMS];
uint32_t nodes;
struct link_pair_st link_pair[16];// enough? only in_conherent
uint32_t link_pair_num;
uint32_t ht_c_num;
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
} __attribute__((packed));
#endif /* AMDK8_PRE_F_H */

2
src/northbridge/amd/amdk8/misc_control.c
View File

@ -169,7 +169,7 @@ static void misc_control_init(struct device *dev)
*/
cmd_ref = 0x04e20707; /* Registered */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (dcl & DCL_UnBufDimm) {
if (dcl & DCL_UnBuffDimm) {
cmd_ref = 0x000D0701; /* Unbuffered */
}
cmd = pci_read_config32(dev, 0xd4);

187
src/northbridge/amd/amdk8/raminit.c
View File

@ -3,9 +3,6 @@
2004.12 yhlu add D0 support
2005.02 yhlu add E0 memory hole support
*/
#if K8_REV_F_SUPPORT == 1
#include "raminit_f.c"
#else
#include <cpu/x86/mem.h>
#include <cpu/x86/cache.h>
@ -26,44 +23,23 @@
static void hard_reset(void);
#endif
#if 1
static void setup_resource_map(const unsigned int *register_values, int max)
{
int i;
// print_debug("setting up resource map....");
#if 0
print_debug("\r\n");
#endif
// printk_debug("setting up resource map....");
for (i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
#if 0
#if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
#endif
dev = register_values[i] & ~0xfff;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
#if 0
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2] & ~register_values[i+1];
pci_write_config32(register_values[i], reg);
#endif
}
// print_debug("done.\r\n");
// printk_debug("done.\n");
}
#endif
static int controller_present(const struct mem_controller *ctrl)
{
@ -78,7 +54,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
/* Careful set limit registers before base registers which
contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
@ -547,48 +524,26 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
int i;
int max;
#if 1
if (!controller_present(ctrl)) {
// print_debug("No memory controller present\r\n");
// printk_debug("No memory controller present\n");
return;
}
#endif
print_spew("setting up CPU");
print_spew_hex8(ctrl->node_id);
print_spew(" northbridge registers\r\n");
printk_spew("setting up CPU%02x northbridge registers\n", ctrl->node_id);
max = ARRAY_SIZE(register_values);
for (i = 0; i < max; i += 3) {
device_t dev;
unsigned where;
unsigned long reg;
#if 0
#if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_spew_hex32(register_values[i]);
print_spew(" <-");
print_spew_hex32(register_values[i+2]);
print_spew("\r\n");
#endif
#endif
dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
where = register_values[i] & 0xfff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
#if 0
reg = pci_read_config32(register_values[i]);
reg &= register_values[i+1];
reg |= register_values[i+2];
pci_write_config32(register_values[i], reg);
#endif
}
print_spew("done.\r\n");
printk_spew("done.\n");
}
static void hw_enable_ecc(const struct mem_controller *ctrl)
{
uint32_t dcl, nbcap;
@ -632,7 +587,7 @@ static int is_registered(const struct mem_controller *ctrl)
*/
uint32_t dcl;
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
return !(dcl & DCL_UnBufDimm);
return !(dcl & DCL_UnBuffDimm);
}
struct dimm_size {
@ -720,7 +675,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
goto out;
val_err:
die("Bad SPD value\r\n");
die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@ -895,9 +850,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
}
/* Report the amount of memory. */
print_spew("RAM: 0x");
print_spew_hex32(tom_k);
print_spew(" KB\r\n");
printk_spew("RAM: 0x%08x kB\n", tom_k);
/* Now set top of memory */
msr_t msr;
@ -992,7 +945,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
if (common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
/* The size differed fail */
/* The cs_mode differed fail */
if (common_cs_mode != cs_mode) {
return 0;
}
@ -1012,7 +965,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
if (is_dual_channel(ctrl)) {
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
// print_debug("8 4GB chip selects cannot be interleaved\r\n");
// printk_debug("8 4GB chip selects cannot be interleaved\n");
return 0;
}
csbase_inc <<=1;
@ -1022,7 +975,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
if (is_dual_channel(ctrl)) {
if ( (bits==3) && (common_cs_mode > 8)) {
// print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
// printk_debug("8 cs_mode>8 chip selects cannot be interleaved\n");
return 0;
}
csbase_inc <<=1;
@ -1049,7 +1002,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
csbase += csbase_inc;
}
print_spew("Interleaved\r\n");
printk_spew("Interleaved\n");
/* Return the memory size in K */
return common_size << (15 + bits);
@ -1062,12 +1015,12 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
/* Remember which registers we have used in the high 8 bits of tom */
tom = 0;
for (;;) {
/* Find the largest remaining canidate */
unsigned index, canidate;
/* Find the largest remaining candidate */
unsigned index, candidate;
uint32_t csbase, csmask;
unsigned size;
csbase = 0;
canidate = 0;
candidate = 0;
for (index = 0; index < 8; index++) {
uint32_t value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
@ -1086,11 +1039,12 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
if (tom & (1 << (index + 24))) {
continue;
}
/* I have a new canidate */
/* I have a new candidate */
csbase = value;
canidate = index;
candidate = index;
}
/* See if I have found a new canidate */
/* See if I have found a new candidate */
if (csbase == 0) {
break;
}
@ -1099,7 +1053,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
size = csbase >> 21;
/* Remember I have used this register */
tom |= (1 << (canidate + 24));
tom |= (1 << (candidate + 24));
/* Recompute the cs base register value */
csbase = (tom << 21) | 1;
@ -1112,9 +1066,9 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
csmask |= 0xfe00; /* For now don't optimize */
/* Write the new base register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
/* Write the new mask register */
pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
pci_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
}
/* Return the memory size in K */
@ -1149,12 +1103,14 @@ static void order_dimms(const struct mem_controller *ctrl)
read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl);
} else {
print_debug("Interleaving disabled\r\n");
printk_debug("Interleaving disabled\n");
tom_k = 0;
}
if (!tom_k) {
tom_k = order_chip_selects(ctrl);
}
/* Compute the memory base address */
base_k = memory_end_k(ctrl, ctrl->node_id);
tom_k += base_k;
@ -1164,16 +1120,15 @@ static void order_dimms(const struct mem_controller *ctrl)
static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
{
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("\r\n");
printk_debug("disabling dimm %02x\n", index);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
dimm_mask &= ~(1 << index);
return dimm_mask;
}
static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask)
static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
long dimm_mask)
{
int i;
int registered;
@ -1191,6 +1146,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
if (value < 0) {
return -1;
}
/* Registered dimm ? */
if (value & (1 << 1)) {
registered = 1;
@ -1205,10 +1161,10 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
}
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_UnBufDimm;
dcl &= ~DCL_UnBuffDimm;
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
dcl |= DCL_UnBufDimm; /* set DCL_DualDIMMen too? */
dcl |= DCL_UnBuffDimm; /* set DCL_DualDIMMen too? */
/* set DCL_En2T if you have non-equal DDR mem types! */
@ -1217,17 +1173,17 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
dcl |= DCL_UpperCSMap;
}
} else {
dcl |= DCL_UnBufDimm;
dcl |= DCL_UnBuffDimm;
}
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
#if 0
if (is_registered(ctrl)) {
print_debug("Registered\r\n");
printk_spew("Registered\n");
} else {
print_debug("Unbuffered\r\n");
printk_spew("Unbuffered\n");
}
#endif
return dimm_mask;
}
@ -1320,7 +1276,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
}
}
}
print_spew("Enabling dual channel memory\r\n");
printk_spew("Enabling dual channel memory\n");
uint32_t dcl;
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_32ByteEn;
@ -1350,7 +1306,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
{
static const struct mem_param speed[] = {
{
.name = "100Mhz\r\n",
.name = "100Mhz",
.cycle_time = 0xa0,
.divisor = (10 <<1),
.tRC = 0x46,
@ -1364,7 +1320,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
},
{
.name = "133Mhz\r\n",
.name = "133Mhz",
.cycle_time = 0x75,
.divisor = (7<<1)+1,
.tRC = 0x41,
@ -1378,7 +1334,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
},
{
.name = "166Mhz\r\n",
.name = "166Mhz",
.cycle_time = 0x60,
.divisor = (6<<1),
.tRC = 0x3C,
@ -1392,7 +1348,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
},
{
.name = "200Mhz\r\n",
.name = "200Mhz",
.cycle_time = 0x50,
.divisor = (5<<1),
.tRC = 0x37,
@ -1418,10 +1374,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
if (!param->cycle_time) {
die("min_cycle_time to low");
}
print_spew(param->name);
#ifdef DRAM_MIN_CYCLE_TIME
print_debug(param->name);
#endif
printk_spew("%s\n", param->name);
return param;
}
@ -1530,6 +1483,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
if (!(dimm_mask & (1 << i))) {
continue;
}
latencies = spd_read_byte(ctrl->channel0[i], 18);
if (latencies < 0) goto hw_error;
if (latencies == 0) {
@ -1610,6 +1564,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
/* Update DRAM Timing Low with our selected cas latency */
value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
@ -1941,7 +1896,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *
clocks = param->dtl_trwt[lat][mtype];
if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
die("Unknown Trwt\r\n");
die("Unknown Trwt\n");
}
dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
@ -2114,7 +2069,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
long dimm_mask;
#if 1
if (!controller_present(ctrl)) {
// print_debug("No memory controller present\r\n");
// printk_debug("No memory controller present\n");
return;
}
#endif
@ -2122,7 +2077,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
activate_spd_rom(ctrl);
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
print_debug("No memory for this cpu\r\n");
printk_debug("No memory for this cpu\n");
return;
}
dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
@ -2146,7 +2101,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
return;
hw_spd_err:
/* Unrecoverable error reading SPD data */
print_err("SPD error - reset\r\n");
print_err("SPD error - reset\n");
hard_reset();
return;
}
@ -2272,7 +2227,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Error if I don't have memory */
if (memory_end_k(ctrl, controllers) == 0) {
die("No memory\r\n");
die("No memory\n");
}
/* Before enabling memory start the memory clocks */
@ -2294,11 +2249,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
}
/* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
/* And if necessary toggle the the reset on the dimms by hand */
memreset(controllers, ctrl);
/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
for (i = 0; i < controllers; i++) {
uint32_t dcl, dch;
if (!controller_present(ctrl + i))
@ -2313,7 +2267,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
if (dcl & DCL_DimmEccEn) {
uint32_t mnc;
print_spew("ECC enabled\r\n");
printk_spew("ECC enabled\n");
mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
mnc |= MNC_ECC_EN;
if (dcl & DCL_128BitEn) {
@ -2329,8 +2283,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dcl &= ~DCL_QFC_EN;
dcl |= DCL_DramInit;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
for (i = 0; i < controllers; i++) {
uint32_t dcl, dch;
if (!controller_present(ctrl + i))
@ -2341,18 +2295,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
continue;
}
print_debug("Initializing memory: ");
printk_debug("Initializing memory: ");
int loops = 0;
do {
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
loops += 1;
loops++;
if ((loops & 1023) == 0) {
print_debug(".");
printk_debug(".");
}
} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
if (loops >= TIMEOUT_LOOPS) {
print_debug(" failed\r\n");
printk_debug(" failed\n");
continue;
}
@ -2365,7 +2318,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
}
print_debug(" done\r\n");
printk_debug(" done\n");
}
#if HW_MEM_HOLE_SIZEK != 0
@ -2384,29 +2337,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
*/
#if USE_DCACHE_RAM == 0
/* Make certain the first 1M of memory is intialized */
print_debug("Clearing initial memory region: ");
/* Use write combine caching while we setup the first 1M */
cache_lbmem(MTRR_TYPE_WRCOMB);
/* clear memory 1meg */
clear_memory((void *)0, CONFIG_LB_MEM_TOPK << 10);
/* The first 1M is now setup, use it */
cache_lbmem(MTRR_TYPE_WRBACK);
print_debug(" done\r\n");
#endif
}
#if USE_DCACHE_RAM == 1
static void set_sysinfo_in_ram(unsigned val)
{
}
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
const uint16_t *spd_addr)
{
int i;
int j;
@ -2427,6 +2365,3 @@ static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const
}
}
}
#endif
#endif

51
src/northbridge/amd/amdk8/raminit_f.c
View File

@ -712,11 +712,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
printk_spew("done.\n");
}
static int is_dual_channel(const struct mem_controller *ctrl)
{
uint32_t dcl;
@ -724,7 +722,6 @@ static int is_dual_channel(const struct mem_controller *ctrl)
return dcl & DCL_Width128;
}
static int is_opteron(const struct mem_controller *ctrl)
{
/* Test to see if I am an Opteron.
@ -738,7 +735,6 @@ static int is_opteron(const struct mem_controller *ctrl)
return !!(nbcap & NBCAP_128Bit);
}
static int is_registered(const struct mem_controller *ctrl)
{
/* Test to see if we are dealing with registered SDRAM.
@ -834,7 +830,8 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
static void set_dimm_size(const struct mem_controller *ctrl,
struct dimm_size *sz, unsigned index, struct mem_info *meminfo)
struct dimm_size *sz, unsigned index,
struct mem_info *meminfo)
{
uint32_t base0, base1;
@ -1014,7 +1011,6 @@ static long spd_set_ram_size(const struct mem_controller *ctrl,
return meminfo->dimm_mask;
}
static void route_dram_accesses(const struct mem_controller *ctrl,
unsigned long base_k, unsigned long limit_k)
{
@ -1045,7 +1041,6 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
}
}
static void set_top_mem(unsigned tom_k, unsigned hole_startk)
{
/* Error if I don't have memory */
@ -1056,9 +1051,9 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
/* Report the amount of memory. */
printk_debug("RAM: 0x%08x kB\n", tom_k);
/* Now set top of memory */
msr_t msr;
if (tom_k > (4*1024*1024)) {
/* Now set top of memory */
msr.lo = (tom_k & 0x003fffff) << 10;
msr.hi = (tom_k & 0xffc00000) >> 22;
wrmsr(TOP_MEM2, msr);
@ -1161,7 +1156,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
csbase_inc <<=1;
}
/* Compute the initial values for csbase and csbask.
* In csbase just set the enable bit and the base to zero.
* In csmask set the mask bits for the size and page level interleave.
@ -1189,6 +1183,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
/* Return the memory size in K */
return common_size << ((27-10) + bits);
}
static unsigned long order_chip_selects(const struct mem_controller *ctrl)
{
unsigned long tom;
@ -1278,7 +1273,6 @@ unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
return end_k;
}
static void order_dimms(const struct mem_controller *ctrl,
struct mem_info *meminfo)
{
@ -1303,7 +1297,6 @@ static void order_dimms(const struct mem_controller *ctrl,
set_top_mem(tom_k, 0);
}
static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
struct mem_info *meminfo)
{
@ -1326,7 +1319,6 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
return meminfo->dimm_mask;
}
static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
struct mem_info *meminfo)
{
@ -1380,17 +1372,14 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
#if 1
if (meminfo->is_registered) {
printk_debug("Registered\n");
printk_spew("Registered\n");
} else {
printk_debug("Unbuffered\n");
printk_spew("Unbuffered\n");
}
#endif
return meminfo->dimm_mask;
}
static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
{
unsigned dimm_mask;
@ -1624,7 +1613,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
if (!param->cycle_time) {
die("min_cycle_time to low");
}
printk_debug("%s\n", param->name);
printk_spew("%s\n", param->name);
return param;
}
@ -2088,7 +2077,6 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
return 1;
}
static int update_dimm_Trcd(const struct mem_controller *ctrl,
const struct mem_param *param, int i, long dimm_mask)
{
@ -2126,17 +2114,14 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_
if (clocks < DTL_TRAS_MIN) {
clocks = DTL_TRAS_MIN;
}
if (clocks > DTL_TRAS_MAX) {
return 0;
}
dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
if (old_clocks >= clocks) { // someone did it?
return 1;
}
dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
@ -2201,7 +2186,6 @@ static int update_dimm_Tref(const struct mem_controller *ctrl,
return 1;
}
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
@ -2235,7 +2219,6 @@ static void set_4RankRDimm(const struct mem_controller *ctrl,
#endif
}
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
struct mem_info *meminfo)
{
@ -2363,7 +2346,6 @@ static void set_DramTerm(const struct mem_controller *ctrl,
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
static void set_ecc(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
@ -2456,19 +2438,16 @@ static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
}
static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
{
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
}
static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
{
set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
}
static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
{
static const uint8_t faw_1k[] = {8, 10, 13, 14};
@ -2486,10 +2465,8 @@ static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *
}
set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
}
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
{
uint32_t dch;
@ -2507,7 +2484,6 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_SlowAccessMode(const struct mem_controller *ctrl)
{
uint32_t dch;
@ -2519,7 +2495,6 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl)
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
/*
DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
DRAM_ADDR_TIMING_CTRL 04, 0x24
@ -2724,7 +2699,6 @@ static void set_RDqsEn(const struct mem_controller *ctrl,
#endif
}
static void set_idle_cycle_limit(const struct mem_controller *ctrl,
const struct mem_param *param)
{
@ -2737,14 +2711,12 @@ static void set_idle_cycle_limit(const struct mem_controller *ctrl,
pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
}
static void set_RdWrQByp(const struct mem_controller *ctrl,
const struct mem_param *param)
{
set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
}
static long spd_set_dram_timing(const struct mem_controller *ctrl,
const struct mem_param *param,
struct mem_info *meminfo)
@ -3058,14 +3030,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
/* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
memreset(controllers, ctrl);
#if 0
printk_debug("prepare to InitDram:");
for (i=0; i<10; i++) {
printk_debug("%08x", i);
print_debug("\b\b\b\b\b\b\b\b");
}
printk_debug("\n");
#endif
/* lets override the rest of the routine */
if (suspend) {
@ -3241,7 +3205,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
}
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
const uint16_t *spd_addr)
{