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x86 romstage: Move stack just below RAMTOP 

Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.

Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2014-10-16 12:47:25 +03:00
parent d05d0db0d0
commit 1729cd8574
18 changed files with 10 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/init/crt0_romcc_epilogue.inc
View File

@ -11,7 +11,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* clear direction flag */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

1
src/arch/x86/init/prologue.inc
View File

@ -18,7 +18,6 @@
*/
#include <cpu/x86/post_code.h>
#include <cpu/x86/stack.h>
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits

3
src/cpu/intel/car/cache_as_ram.inc
View File

@ -21,7 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic_def.h>
@ -361,7 +360,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@ -20,7 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@ -430,7 +429,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

1
src/cpu/intel/haswell/cache_as_ram.inc
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>

3
src/cpu/intel/haswell/romstage.c
View File

@ -25,7 +25,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/stack.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
@ -85,7 +84,7 @@ static unsigned long choose_top_of_stack(void)
ROMSTAGE_RAM_STACK_SIZE);
stack_top += ROMSTAGE_RAM_STACK_SIZE;
#else
stack_top = ROMSTAGE_STACK;
stack_top = CONFIG_RAMTOP;
#endif
return stack_top;
}

3
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@ -278,7 +277,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@ -311,7 +310,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@ -224,7 +223,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/via/car/cache_as_ram.inc
View File

@ -25,7 +25,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <console/post_codes.h>
@ -268,7 +267,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

1
src/drivers/intel/fsp/cache_as_ram.inc
View File

@ -19,7 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>

3
src/drivers/intel/fsp/fsp_util.c
View File

@ -19,7 +19,6 @@
#include <types.h>
#include <string.h>
#include <cpu/x86/stack.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
@ -81,7 +80,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
#endif
memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
FspRtBuffer.Common.StackTop = (u32 *)ROMSTAGE_STACK;
FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
FspInitParams.NvsBufferPtr = NULL;
#if IS_ENABLED(CONFIG_FSP_USES_UPD)

32
src/include/cpu/x86/stack.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __CPU_X86_STACK_H
#define __CPU_X86_STACK_H
/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
* makes sure that we stay completely within the 1M-64K of memory that we
* preserve for suspend/resume. This is basically HIGH_MEMORY_SAFE (see
* cbmem.h)
*/
#define ROMSTAGE_STACK_OFFSET ( (1024 - 64) * 1024 )
#define ROMSTAGE_STACK (CONFIG_RAMBASE + ROMSTAGE_STACK_OFFSET)
#endif

3
src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@ -63,7 +62,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

1
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
View File

@ -19,7 +19,6 @@
#include <types.h>
#include <string.h>
#include <cpu/x86/stack.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>

1
src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
View File

@ -19,7 +19,6 @@
#include <types.h>
#include <string.h>
#include <cpu/x86/stack.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>

1
src/soc/intel/baytrail/romstage/cache_as_ram.inc
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>

1
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
View File

@ -19,7 +19,6 @@
#include <types.h>
#include <string.h>
#include <cpu/x86/stack.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>