mb/google/volteer: Pull up GPP_D16 instead of driving it

The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to
GPP_D16 but there is a RTS5261 requirement to pull up this pin and not
drive it at power on. We can meet this requirement without breaking
other boards by changing GPP_D16 to be a no-connect with an internal
pull up. Other boards use this signal as an enable input, so changing
this to pull up is OK.

BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
	can read SD cards.

Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Caveh Jalali 2020-08-01 16:29:27 -07:00 committed by Nick Vaccaro
parent 0c1879ff38
commit 173493784d
2 changed files with 2 additions and 2 deletions

View File

@ -91,7 +91,7 @@ static const struct pad_config override_gpio_table[] = {
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_D16, 1, DEEP), PAD_NC(GPP_D16, UP_20K),
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */ /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
PAD_CFG_GPO(GPP_D17, 1, DEEP), PAD_CFG_GPO(GPP_D17, 1, DEEP),
/* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */

View File

@ -91,7 +91,7 @@ static const struct pad_config override_gpio_table[] = {
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_D16, 1, DEEP), PAD_NC(GPP_D16, UP_20K),
/* D17 : ISH_GP4 ==> EN_FCAM_PWR */ /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
PAD_CFG_GPO(GPP_D17, 1, DEEP), PAD_CFG_GPO(GPP_D17, 1, DEEP),
/* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */