Add Intel i5000 Memory Controller Hub
Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/491 Tested-by: build bot (Jenkins)
This commit is contained in:
Sven Schnelle
parent
f61ad93bc9
commit
17670866a0
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@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
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source src/northbridge/intel/i855/Kconfig
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source src/northbridge/intel/i945/Kconfig
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source src/northbridge/intel/sch/Kconfig
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source src/northbridge/intel/i5000/Kconfig
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@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
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@ -0,0 +1,26 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config NORTHBRIDGE_INTEL_I5000
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bool
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select HAVE_DEBUG_RAM_SETUP
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config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
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bool
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prompt "Run ramcheck after RAM initialization"
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@ -0,0 +1,21 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2009 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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driver-y += northbridge.c
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romstage-y += raminit.c udelay.c
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct northbridge_intel_i5000_config {
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};
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extern struct chip_operations northbridge_intel_i5000_ops;
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@ -0,0 +1,188 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include <cpu/cpu.h>
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#include <boot/tables.h>
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#include <arch/acpi.h>
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#include <cbmem.h>
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#include "chip.h"
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static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations intel_pci_ops = {
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.set_subsystem = intel_set_subsystem,
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};
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static struct device_operations mc_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.scan_bus = 0,
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.ops_pci = &intel_pci_ops,
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};
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static const struct pci_driver mc_driver __pci_driver = {
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.ops = &mc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x25d8,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(dev->link_list);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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#if CONFIG_WRITE_HIGH_TABLES
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#include <cbmem.h>
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#endif
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static void pci_domain_set_resources(device_t dev)
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{
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struct resource *resource;
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uint32_t hecbase, amsize, tolm;
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uint64_t ambase, memsize;
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int idx = 0;
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device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
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device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
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tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
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hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
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hecbase &= 0xffff;
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ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
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(u64)pci_read_config32(dev16_0, 0x4c) << 32);
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amsize = pci_read_config32(dev16_0, 0x50);
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ambase &= 0x000000ffffff0000;
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printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
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/* Report the memory regions */
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
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memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
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pci_read_config16(dev16_1, 0x84) & ~3);
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memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
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memsize <<= 24;
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printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
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if (memsize > 0xe0000000) {
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memsize -= 0xe0000000;
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printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
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ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
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}
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if (hecbase) {
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printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
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resource = new_resource(dev, idx++);
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resource->base = (resource_t)(uint64_t)hecbase << 28;
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resource->size = (resource_t)256 * 1024 * 1024;
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resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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resource = new_resource(dev, idx++);
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resource->base = (resource_t)(uint64_t)0xffe00000;
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resource->size = (resource_t)0x200000;
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resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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if (ambase && amsize) {
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resource = new_resource(dev, idx++);
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resource->base = (resource_t)ambase;
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resource->size = (resource_t)amsize;
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resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
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various fixed address registers (BOFL, SPAD, SPADS */
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resource = new_resource(dev, idx++);
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resource->base = (resource_t)0xfe600000;
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resource->size = (resource_t)0x00100000;
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resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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assign_resources(dev->link_list);
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#if CONFIG_WRITE_HIGH_TABLES
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/* Leave some space for ACPI, PIRQ and MP tables */
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high_tables_base = tolm - HIGH_MEMORY_SIZE;
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high_tables_size = HIGH_MEMORY_SIZE;
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printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
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#endif
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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#if CONFIG_MMCONF_SUPPORT_DEFAULT
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.ops_pci_bus = &pci_ops_mmconf,
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#else
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.ops_pci_bus = &pci_cf8_conf1,
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#endif
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};
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static void enable_dev(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_i5000_ops = {
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CHIP_NAME("Intel i5000 Northbridge")
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.enable_dev = enable_dev,
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};
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,337 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef NORTHBRIDGE_I5000_RAMINIT_H
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#define NORTHBRIDGE_I5000_RAMINIT_H
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#include <types.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#define I5000_MAX_BRANCH 2
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#define I5000_MAX_CHANNEL 2
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#define I5000_MAX_DIMM_PER_CHANNEL 4
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#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
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#define I5000_FBDRST 0x53
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#define I5000_SPD_BUSY (1 << 12)
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#define I5000_SPD_SBE (1 << 13)
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#define I5000_SPD_WOD (1 << 14)
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#define I5000_SPD_RDO (1 << 15)
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#define I5000_SPD0 0x74
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#define I5000_SPD1 0x76
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#define I5000_SPDCMD0 0x78
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#define I5000_SPDCMD1 0x7c
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#define I5000_FBDHPC 0x4f
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#define I5000_FBDST 0x4b
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#define I5000_FBDHPC_STATE_RESET 0x00
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#define I5000_FBDHPC_STATE_INIT 0x10
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#define I5000_FBDHPC_STATE_READY 0x20
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#define I5000_FBDHPC_STATE_ACTIVE 0x30
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#define I5000_FBDISTS0 0x58
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#define I5000_FBDISTS1 0x5a
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#define I5000_FBDLVL0 0x44
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#define I5000_FBDLVL1 0x45
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#define I5000_FBDICMD0 0x46
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#define I5000_FBDICMD1 0x47
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#define I5000_FBDICMD_IDLE 0x00
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#define I5000_FBDICMD_TS0 0x80
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#define I5000_FBDICMD_TS1 0x90
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#define I5000_FBDICMD_TS2 0xa0
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#define I5000_FBDICMD_TS3 0xb0
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#define I5000_FBDICMD_TS2_MERGE 0xd0
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#define I5000_FBDICMD_TS2_NOMERGE 0xe0
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#define I5000_FBDICMD_ALL_ONES 0xf0
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#define I5000_AMBPRESENT0 0x64
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#define I5000_AMBPRESENT1 0x66
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#define I5000_FBDSBTXCFG0 0xc0
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#define I5000_FBDSBTXCFG1 0xc1
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#define I5000_PROCENABLE 0xf0
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#define I5000_FBD0IBPORTCTL 0x180
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#define I5000_FBD0IBTXPAT2EN 0x1a8
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#define I5000_FBD0IBRXPAT2EN 0x1ac
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#define I5000_FBD0IBTXMSK 0x18c
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#define I5000_FBD0IBRXMSK 0x190
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#define I5000_FBDPLLCTRL 0x1c0
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/* dev 16, function 1 registers */
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#define I5000_MC 0x40
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#define I5000_DRTA 0x48
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#define I5000_DRTB 0x4c
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#define I5000_ERRPERR 0x50
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#define I5000_MCA 0x58
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#define I5000_TOLM 0x6c
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#define I5000_MIR0 0x80
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#define I5000_MIR1 0x84
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#define I5000_MIR2 0x88
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#define I5000_AMIR0 0x8c
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#define I5000_AMIR1 0x90
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#define I5000_AMIR2 0x94
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#define I5000_FERR_FAT_FBD 0x98
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#define I5000_NERR_FAT_FBD 0x9c
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#define I5000_FERR_NF_FBD 0xa0
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#define I5000_NERR_NF_FBD 0xa4
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#define I5000_EMASK_FBD 0xa8
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#define I5000_ERR0_FBD 0xac
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#define I5000_ERR1_FBD 0xb0
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#define I5000_ERR2_FBD 0xb4
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#define I5000_MCERR_FBD 0xb8
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#define I5000_NRECMEMA 0xbe
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#define I5000_NRECMEMB 0xc0
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#define I5000_NRECFGLOG 0xc4
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#define I5000_NRECMEMA 0xbe
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#define I5000_NRECFBDA 0xc8
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#define I5000_NRECFBDB 0xcc
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#define I5000_NRECFBDC 0xd0
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#define I5000_NRECFBDD 0xd4
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#define I5000_NRECFBDE 0xd8
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#define I5000_REDMEMB 0x7c
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#define I5000_RECMEMA 0xe2
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#define I5000_RECMEMB 0xe4
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#define I5000_RECFGLOG 0xe8
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#define I5000_RECFBDA 0xec
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#define I5000_RECFBDB 0xf0
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#define I5000_RECFBDC 0xf4
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#define I5000_RECFBDD 0xf8
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#define I5000_RECFBDE 0xfc
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#define I5000_FBDTOHOSTGRCFG0 0x160
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#define I5000_FBDTOHOSTGRCFG1 0x164
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#define I5000_HOSTTOFBDGRCFG 0x168
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#define I5000_GRFBDLVLDCFG 0x16c
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#define I5000_GRHOSTFULLCFG 0x16d
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#define I5000_GRBUBBLECFG 0x16e
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#define I5000_GRFBDTOHOSTDBLCFG 0x16f
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/* dev 16, function 2 registers */
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#define I5000_FERR_GLOBAL 0x40
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#define I5000_NERR_GLOBAL 0x44
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/* dev 21, function 0 registers */
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#define I5000_MTR0 0x80
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#define I5000_MTR1 0x84
|
||||
#define I5000_MTR2 0x88
|
||||
#define I5000_MTR3 0x8c
|
||||
#define I5000_DMIR0 0x90
|
||||
#define I5000_DMIR1 0x94
|
||||
#define I5000_DMIR2 0x98
|
||||
#define I5000_DMIR3 0x9c
|
||||
#define I5000_DMIR4 0xa0
|
||||
|
||||
#define DEFAULT_AMBASE 0xfe000000
|
||||
|
||||
/* AMB function 1 registers */
|
||||
#define AMB_FBDSBCFGNXT 0x54
|
||||
#define AMB_FBDLOCKTO 0x68
|
||||
#define AMB_EMASK 0x8c
|
||||
#define AMB_FERR 0x90
|
||||
#define AMB_NERR 0x94
|
||||
#define AMB_CMD2DATANXT 0xe8
|
||||
|
||||
/* AMB function 3 registers */
|
||||
#define AMB_DAREFTC 0x70
|
||||
#define AMB_DSREFTC 0x74
|
||||
#define AMB_DRT 0x78
|
||||
#define AMB_DRC 0x7c
|
||||
|
||||
#define AMB_MBCSR 0x40
|
||||
#define AMB_MBADDR 0x44
|
||||
#define AMB_MBLFSRSED 0xa4
|
||||
|
||||
/* AMB function 4 registers */
|
||||
#define AMB_DCALCSR 0x40
|
||||
#define AMB_DCALADDR 0x44
|
||||
#define AMB_DCALCSR_START (1 << 31)
|
||||
|
||||
#define AMB_DCALCSR_OPCODE_NOP 0x00
|
||||
#define AMB_DCALCSR_OPCODE_REFRESH 0x01
|
||||
#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02
|
||||
#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03
|
||||
#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05
|
||||
#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c
|
||||
#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
|
||||
|
||||
#define AMB_DDR2ODTC 0xfc
|
||||
|
||||
#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
|
||||
#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
|
||||
#define FBDIMM_SPD_FTB 0x08
|
||||
#define FBDIMM_SPD_MTB_DIVIDEND 0x09
|
||||
#define FBDIMM_SPD_MTB_DIVISOR 0x0a
|
||||
#define FBDIMM_SPD_MIN_TCK 0x0b
|
||||
#define FBDIMM_SPD_CAS_LATENCIES 0x0d
|
||||
#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
|
||||
#define FBDIMM_SPD_T_WR 0x10
|
||||
#define FBDIMM_SPD_T_RCD 0x13
|
||||
#define FBDIMM_SPD_T_RRD 0x14
|
||||
#define FBDIMM_SPD_T_RP 0x15
|
||||
#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
|
||||
#define FBDIMM_SPD_T_RAS 0x17
|
||||
#define FBDIMM_SPD_T_RC 0x18
|
||||
#define FBDIMM_SPD_T_RFC 0x19
|
||||
#define FBDIMM_SPD_T_WTR 0x1b
|
||||
#define FBDIMM_SPD_T_RTP 0x1c
|
||||
#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
|
||||
#define FBDIMM_SPD_ODT 0x4f
|
||||
#define FBDIMM_SPD_T_REFI 0x20
|
||||
#define FBDIMM_SPD_T_BB 0x83
|
||||
#define FBDIMM_SPD_CMD2DATA_800 0x54
|
||||
#define FBDIMM_SPD_CMD2DATA_667 0x55
|
||||
#define FBDIMM_SPD_CMD2DATA_533 0x56
|
||||
|
||||
void i5000_fbdimm_init(void);
|
||||
|
||||
#define I5000_BURST4 0x01
|
||||
#define I5000_BURST8 0x02
|
||||
#define I5000_BURST_CHOP 0x80
|
||||
|
||||
#define I5000_ODT_50 4
|
||||
#define I5000_ODT_75 2
|
||||
#define I5000_ODT_150 1
|
||||
|
||||
enum ddr_speeds {
|
||||
DDR_533MHZ,
|
||||
DDR_667MHZ,
|
||||
DDR_MAX,
|
||||
};
|
||||
|
||||
struct i5000_fbdimm {
|
||||
struct i5000_fbd_branch *branch;
|
||||
struct i5000_fbd_channel *channel;
|
||||
struct i5000_fbd_setup *setup;
|
||||
enum ddr_speeds speed;
|
||||
int num;
|
||||
int present:1;
|
||||
u32 ambase;
|
||||
|
||||
/* SPD data */
|
||||
u8 amb_personality_bytes[14];
|
||||
u8 banks;
|
||||
u8 rows;
|
||||
u8 columns;
|
||||
u8 ranks;
|
||||
u8 odt;
|
||||
u8 sdram_width;
|
||||
u8 mtb_divisor;
|
||||
u8 mtb_dividend;
|
||||
u8 t_ck_min;
|
||||
u8 min_cas_latency;
|
||||
u8 t_rrd;
|
||||
u16 t_rfc;
|
||||
u8 t_wtr;
|
||||
u8 t_refi;
|
||||
u8 cmd2datanxt[DDR_MAX];
|
||||
|
||||
u16 vendor;
|
||||
u16 device;
|
||||
|
||||
/* memory rank size in MB */
|
||||
int ranksize;
|
||||
};
|
||||
|
||||
struct i5000_fbd_channel {
|
||||
struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
|
||||
struct i5000_fbd_branch *branch;
|
||||
struct i5000_fbd_setup *setup;
|
||||
int num;
|
||||
int used;
|
||||
int highest_amb;
|
||||
int columns;
|
||||
int rows;
|
||||
int ranks;
|
||||
int banks;
|
||||
int width;
|
||||
/* memory size in MB on this channel */
|
||||
int totalmem;
|
||||
};
|
||||
|
||||
struct i5000_fbd_branch {
|
||||
struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
|
||||
struct i5000_fbd_setup *setup;
|
||||
device_t branchdev;
|
||||
int num;
|
||||
int used;
|
||||
/* memory size in MB on this branch */
|
||||
int totalmem;
|
||||
};
|
||||
|
||||
enum odt {
|
||||
ODT_150OHM=1,
|
||||
ODT_50OHM=4,
|
||||
ODT_75OHM=2,
|
||||
};
|
||||
|
||||
enum bl {
|
||||
BL_BL4=1,
|
||||
BL_BL8=2,
|
||||
};
|
||||
|
||||
struct i5000_fbd_setup {
|
||||
struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
|
||||
struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
|
||||
enum bl bl;
|
||||
enum ddr_speeds ddr_speed;
|
||||
|
||||
int single_channel:1;
|
||||
u32 tolm;
|
||||
|
||||
/* global SDRAM timing parameters */
|
||||
u8 t_al;
|
||||
u8 t_cl;
|
||||
u8 t_ras;
|
||||
u8 t_wrc;
|
||||
u8 t_rc;
|
||||
u8 t_rfc;
|
||||
u8 t_rrd;
|
||||
u8 t_ref;
|
||||
u8 t_w2rdr;
|
||||
u8 t_r2w;
|
||||
u8 t_w2r;
|
||||
u8 t_r2r;
|
||||
u8 t_w2w;
|
||||
u8 t_wtr;
|
||||
u8 t_rcd;
|
||||
u8 t_rp;
|
||||
u8 t_wr;
|
||||
u8 t_rtp;
|
||||
/* memory size in MB */
|
||||
int totalmem;
|
||||
};
|
||||
|
||||
int mainboard_set_fbd_clock(int);
|
||||
#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff)))
|
||||
#endif
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <delay.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/x86/tsc.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <console/console.h>
|
||||
/**
|
||||
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
|
||||
*/
|
||||
|
||||
void udelay(u32 us)
|
||||
{
|
||||
u32 dword;
|
||||
tsc_t tsc, tsc1, tscd;
|
||||
msr_t msr;
|
||||
u32 fsb = 0, divisor;
|
||||
u32 d; /* ticks per us */
|
||||
u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
|
||||
|
||||
msr = rdmsr(0xcd);
|
||||
switch (msr.lo & 0x07) {
|
||||
case 5:
|
||||
fsb = 400;
|
||||
break;
|
||||
case 1:
|
||||
fsb = 533;
|
||||
break;
|
||||
case 3:
|
||||
fsb = 667;
|
||||
break;
|
||||
case 2:
|
||||
fsb = 800;
|
||||
break;
|
||||
case 0:
|
||||
fsb = 1067;
|
||||
break;
|
||||
case 4:
|
||||
fsb = 1333;
|
||||
break;
|
||||
case 6:
|
||||
fsb = 1600;
|
||||
break;
|
||||
}
|
||||
|
||||
msr = rdmsr(0x198);
|
||||
divisor = (msr.hi >> 8) & 0x1f;
|
||||
|
||||
d = fsb * divisor;
|
||||
|
||||
tscd.hi = us / dn;
|
||||
tscd.lo = (us - tscd.hi * dn) * d;
|
||||
|
||||
tsc1 = rdtsc();
|
||||
dword = tsc1.lo + tscd.lo;
|
||||
if ((dword < tsc1.lo) || (dword < tscd.lo)) {
|
||||
tsc1.hi++;
|
||||
}
|
||||
tsc1.lo = dword;
|
||||
tsc1.hi += tscd.hi;
|
||||
|
||||
tsc = rdtsc();
|
||||
|
||||
do {
|
||||
tsc = rdtsc();
|
||||
} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
|
||||
}
|
||||
Loading…
Reference in New Issue