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mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg C 

PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.

BUG=133345634
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Hatch.

Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet Pawnikar 2019-07-23 22:32:17 +05:30 committed by Subrata Banik
parent 810527a4ea
commit 17674ad829
1 changed files with 6 additions and 1 deletions
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7
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -47,6 +47,11 @@ chip soc/intel/cannonlake
# Unlock GPIO pads
register "PchUnlockGpioPads" = "1"
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.
register "common_soc_config.pch_thermal_trip" = "77"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
@ -194,7 +199,7 @@ chip soc/intel/cannonlake
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 05.0 off end # SA IPU
device pci 12.0 off end # Thermal Subsystem
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 14.0 on