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mb/google/rex: Update Rex Flash Layout 

This patch updates the Rex flash layout to allow CSE Lite FW
update and accommodate multiple ESx SoC stepping blobs.

For default chromeos.fmd

SI_BIOS:
     RW_SECTION_A/B: Increased by ~1.9MB.
     RW_LEGACY: Reduce to 1MB.
     RW_MISC: Reduce to 152KB.
        - Drop RW_SPD_CACHE
	- Optimize other sections

Additionally, moved RW_LEGACY under extended BIOS region.

For chromeos-debug-fsp.fmd

SI_BIOS:
     RW_SECTION_A/B: Increased by ~1.2MB.
     RW_LEGACY: Dropped
     RW_MISC: Reduce to 152KB.
        - Drop RW_SPD_CACHE
	- Optimize other sections

BUG=b:262868089
TEST=Able to enable CSE update on google/rex and have free space
to add one more PUNIT FW for support different SoC stepping.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-02-21 12:35:45 +05:30
parent 8c75d4bd4c
commit 1767cd2a69
2 changed files with 27 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/mainboard/google/rex/chromeos-debug-fsp.fmd
View File

@ -4,39 +4,33 @@ FLASH 32M {
SI_ME
}
SI_BIOS 23M {
RW_SECTION_A 7M {
VBLOCK_A 64K
RW_SECTION_A 7604K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 3008K
ME_RW_A(CBFS) 4400K
}
RW_MISC 1M {
RW_MISC 152K {
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 7M {
VBLOCK_B 64K
RW_SECTION_B 7604K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 3008K
ME_RW_B(CBFS) 4400K
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.

34
src/mainboard/google/rex/chromeos.fmd
View File

@ -4,41 +4,35 @@ FLASH 32M {
SI_ME
}
SI_BIOS 23M {
RW_SECTION_A 6M {
VBLOCK_A 64K
RW_SECTION_A 7092K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 3008K
ME_RW_A(CBFS) 4400K
}
RW_LEGACY(CBFS) 2M
RW_MISC 1M {
RW_MISC 152K {
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 6M {
VBLOCK_B 64K
RW_SECTION_B 7092K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 3008K
ME_RW_B(CBFS) 4400K
}
RW_LEGACY(CBFS) 1M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 8M {