From 17721be11a64b82d1d2bb4165bd3bf8380016fdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 21 Dec 2020 17:09:08 +0100 Subject: [PATCH] mb/google/reef: do LPC/eSPI pad configuration at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do LPC/eSPI pad configuration at board-level to match other platforms. This is done by adding missing pads to the bootblock gpio table. The soc code gets dropped in CB:49410. Change-Id: I95993b1bd4f1fd8b4ac7b21fb89ec4d196b0240a Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49412 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/reef/bootblock.c | 2 -- .../google/reef/variants/baseboard/gpio.c | 18 +++++++++++++++++- .../google/reef/variants/coral/gpio.c | 18 +++++++++++++++++- 3 files changed, 34 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index 3e9f51afd0..577dae507d 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include @@ -12,7 +11,6 @@ void bootblock_mainboard_init(void) const struct pad_config *pads; size_t num; - lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); mainboard_ec_init(); diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 28203cfb5a..aec2e988c9 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -60,7 +60,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ - /* LPC */ + /* + * LPC + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ @@ -340,11 +343,24 @@ const struct pad_config * __weak variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 87d3529d61..29c41c68dc 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -61,7 +61,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ - /* LPC */ + /* + * LPC + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ @@ -341,11 +344,24 @@ const struct pad_config *variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ };