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soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB 

EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.

BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported

Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nikolai Vyssotski 2021-06-04 10:35:15 -05:00 committed by Raul Rangel
parent 0889a80c63
commit 177a402b6e
2 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/amd/common/fsp/pci/pci_routing_info.c
View File

@ -11,23 +11,27 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries)
{ {
static const struct pci_routing_info *routing_table; static const struct pci_routing_info *routing_table;
static size_t routing_table_entries; static size_t routing_table_entries;
size_t hob_size = 0; size_t hob_size = 0;
const struct {
uint32_t num_of_entries;
struct pci_routing_info routing_table[];
} __packed *routing_hob;
if (routing_table) { if (routing_table) {
*entries = routing_table_entries; *entries = routing_table_entries;
return routing_table; return routing_table;
} }
routing_table = fsp_find_extension_hob_by_guid(AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.b, routing_hob = fsp_find_extension_hob_by_guid(AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.b,
&hob_size); &hob_size);
if (routing_table == NULL || hob_size == 0) { if (routing_hob == NULL || hob_size == 0 || routing_hob->num_of_entries == 0) {
printk(BIOS_ERR, "Couldn't find PCIe routing HOB.\n"); printk(BIOS_ERR, "ERROR: Couldn't find valid PCIe interrupt routing HOB.\n");
return NULL; return NULL;
} }
routing_table_entries = hob_size / sizeof(struct pci_routing_info); routing_table = routing_hob->routing_table;
routing_table_entries = routing_hob->num_of_entries;
for (size_t i = 0; i < routing_table_entries; ++i) { for (size_t i = 0; i < routing_table_entries; ++i) {
printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n", printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n",

4
src/vendorcode/amd/fsp/cezanne/FspGuids.h
View File

@ -14,7 +14,7 @@
0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)
#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \ #define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \
GUID_INIT(0x00D54AA7, 0x0002, 0x47F5, \ GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \
0x00, 0x78, 0x08, 0x57, 0x00, 0x00, 0xA4, 0x11) 0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C )
#endif /* __FSP_GUIDS__ */ #endif /* __FSP_GUIDS__ */