mainboard: Drop `SataMode` setting from Skylake devicetrees

All Skylake mainboards use the default value for the setting `SataMode`.
Thus, drop it from their devicetree.

Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2021-12-05 07:29:17 +01:00
parent ed8081cddd
commit 178153dc45
16 changed files with 0 additions and 16 deletions

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@ -34,7 +34,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataMode" = "0"
# The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"

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@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -66,7 +66,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[1]" = "1"

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@ -36,7 +36,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -44,7 +44,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0" register "SsicPortEnable" = "0"

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@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -44,7 +44,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

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@ -56,7 +56,6 @@ chip soc/intel/skylake
device pci 16.3 off end # ME KT device pci 16.3 off end # ME KT
device pci 16.4 off end # MEI #3 device pci 16.4 off end # MEI #3
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataMode" = "SATA_AHCI"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ register "SataPortsEnable" = "{
[0] = 1, [0] = 1,

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@ -34,7 +34,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1" register "SataPortsEnable[2]" = "1"

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@ -29,7 +29,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "DspEnable" = "0" register "DspEnable" = "0"
register "IoBufferOwnership" = "0" register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0" register "SsicPortEnable" = "0"

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@ -42,7 +42,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "0" register "SataPortsEnable[1]" = "0"
register "SataPortsEnable[2]" = "1" register "SataPortsEnable[2]" = "1"

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@ -23,7 +23,6 @@ chip soc/intel/skylake
# FSP Configuration # FSP Configuration
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"
register "SataPortsEnable[1]" = "0" register "SataPortsEnable[1]" = "0"
register "SataPortsEnable[2]" = "0" register "SataPortsEnable[2]" = "0"