amd/stoneyridge: Move model_15_init.c to cpu.c
Move the remaining model_15_init.c functionality to cpu.c, making it similar to other soc implementations. Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23724 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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@ -92,7 +92,6 @@ ramstage-y += southbridge.c
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ramstage-y += sb_util.c
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ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
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ramstage-y += lpc.c
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ramstage-y += model_15_init.c
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ramstage-y += northbridge.c
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ramstage-y += pmutil.c
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ramstage-y += reset.c
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@ -18,6 +18,7 @@
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/amd/amdfam15.h>
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#include <device/device.h>
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#include <soc/pci_devs.h>
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@ -113,3 +114,33 @@ void stoney_init_cpus(struct device *dev)
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if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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static void model_15_init(device_t dev)
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{
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printk(BIOS_DEBUG, "Model 15 Init.\n");
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int i;
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msr_t msr;
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0 ; i < 6 ; i++)
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wrmsr(MCI_STATUS + (i * 4), msr);
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setup_lapic();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x670f00 },
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -1,59 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/pae.h>
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#include <pc80/mc146818rtc.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/amd/amdfam15.h>
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#include <arch/acpi.h>
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static void model_15_init(device_t dev)
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{
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printk(BIOS_DEBUG, "Model 15 Init.\n");
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int i;
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msr_t msr;
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0 ; i < 6 ; i++)
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wrmsr(MCI_STATUS + (i * 4), msr);
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setup_lapic();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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};
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static const struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x670f00 },
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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