diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 15f9c8d96e..bea4feedbd 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -4,14 +4,20 @@
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 #include <baseboard/variants.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	struct cnl_mb_cfg board_memcfg;
+	const struct pad_config *pads;
+	size_t pads_num;
 
 	variant_mainboard_post_init_params(memupd);
 
 	wilco_ec_romstage_init();
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, get_variant_memory_cfg(&board_memcfg));
+
+	pads = variant_romstage_gpio_table(&pads_num);
+	gpio_configure_pads(pads, pads_num);
 }
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index 6220bf28b7..b008427b7b 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -249,6 +249,12 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 	return early_gpio_table;
 }
 
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
 static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
 	CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
index db0b3a9466..ee48fec46b 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
@@ -28,5 +28,6 @@
 
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_romstage_gpio_table(size_t *num);
 
 #endif