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drop setup_ics code that was blatantly copied from cx700 and 

was mainboard specific and unused there already.

some more minor warning fixes.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-14 17:11:47 +00:00 committed by Stefan Reinauer
parent f4cc089f1e
commit 17b60a985b
6 changed files with 12 additions and 81 deletions
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10
src/mainboard/via/epia-m700/romstage.c
View File

@ -24,6 +24,7 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
#define PAYLOAD_IS_SEABIOS 0
#include <stdint.h>
#include <device/pci_def.h>
@ -85,11 +86,6 @@ static int acpi_is_wakeup_early_via_vx800(void)
return result;
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
/* All content of this function came from the cx700 port of coreboot. */
static void enable_mainboard_devices(void)
{
@ -273,7 +269,8 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
#define gCom1Base 0x3f8
#define gCom2Base 0x2f8
void EmbedComInit(void)
#if 0
static void EmbedComInit(void)
{
u8 ByteVal;
u16 ComBase;
@ -379,6 +376,7 @@ void EmbedComInit(void)
/* SOutput("Embedded COM output\n"); */
/* while(1); */
}
#endif
/* cache_as_ram.inc jumps to here. */
void main(unsigned long bist)

2
src/northbridge/intel/e7501/debug.c
View File

@ -140,7 +140,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int j;
#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
#else`
#else
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".1: ");

4
src/northbridge/via/cn400/vgabios.c
View File

@ -336,7 +336,7 @@ void do_vgabios(void)
{
device_t dev;
unsigned long busdevfn;
unsigned int rom = 0;
u32 rom;
unsigned char *buf;
unsigned int size = 64*1024;
int i;
@ -357,7 +357,7 @@ void do_vgabios(void)
/* declare rom address here - keep any config data out of the way
* of core LXB stuff */
rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
rom = (u32)cbfs_load_optionrom(dev->vendor, dev->device, 0);
pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
printk(BIOS_DEBUG, "VGA BIOS ROM base address: %x\n", rom);

6
src/northbridge/via/vx800/rank_map.c
View File

@ -17,12 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr,
u8 PhyRank, u8 VirRank, BOOLEAN Enable);
extern void SetEndingAddr(DRAM_SYS_ATTR * DramAttr, u8 VirRank, // Ending address register number indicator (INDEX
INT8 Value); // (value) add or subtract value to this and after banks
void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr);
void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr);

8
src/northbridge/via/vx800/vgabios.c
View File

@ -158,6 +158,7 @@ static void real_mode_switch_call_vga(unsigned long devfn)
/* put the stack at the end of page zero.
* that way we can easily share it between real and protected,
* since the 16-bit ESP at segment 0 will work for any case.
*/
/* Setup a stack */
" mov $0x0, %ax \n"
" mov %ax, %ss \n"
@ -240,6 +241,7 @@ void vga_enable_console()
/* put the stack at the end of page zero.
* that way we can easily share it between real and protected,
* since the 16-bit ESP at segment 0 will work for any case.
*/
/* Setup a stack */
" mov $0x0, %ax \n"
" mov %ax, %ss \n"
@ -295,7 +297,7 @@ void do_vgabios(void)
{
device_t dev;
unsigned long busdevfn;
unsigned int rom = 0;
u32 rom;
unsigned char *buf;
unsigned int size = 64 * 1024;
int i;
@ -318,7 +320,7 @@ void do_vgabios(void)
/* declare rom address here - keep any config data out of the way
* of core LXB stuff */
rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
rom = (u32)cbfs_load_optionrom(dev->vendor, dev->device, 0);
pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
printk(BIOS_DEBUG, "rom base: %x\n", rom);
buf = (unsigned char *)rom;
@ -617,7 +619,7 @@ void setup_realmode_idt(void)
TF bit is set upon call to real mode */
idts[1].cs = 0;
idts[1].offset = 16384;
memcpy(16384, &debughandle, &end_debughandle - &debughandle);
memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle);
}

63
src/northbridge/via/vx800/vx800_early_smbus.c
View File

@ -108,62 +108,6 @@ static void smbus_reset(void)
}
/* Public functions */
static unsigned int set_ics_data(unsigned char dev, int data, char len)
{
smbus_reset();
/* clear host data port */
outb(0x00, SMBHSTDAT0);
SMBUS_DELAY();
smbus_wait_until_ready();
/* read to reset block transfer counter */
inb(SMBHSTCTL);
/* fill blocktransfer array */
if (dev == 0xd2) {
//char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
outb(0x0d, SMBBLKDAT);
outb(0x00, SMBBLKDAT);
outb(0x3f, SMBBLKDAT);
outb(0xcd, SMBBLKDAT);
outb(0x7f, SMBBLKDAT);
outb(0xbf, SMBBLKDAT);
outb(0x1a, SMBBLKDAT);
outb(0x2a, SMBBLKDAT);
outb(0x01, SMBBLKDAT);
outb(0x0f, SMBBLKDAT);
outb(0x0b, SMBBLKDAT);
outb(0x80, SMBBLKDAT);
outb(0x8d, SMBBLKDAT);
outb(0x9b, SMBBLKDAT);
} else {
//char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff};
outb(0x08, SMBBLKDAT);
outb(0xff, SMBBLKDAT);
outb(0x3f, SMBBLKDAT);
outb(0x00, SMBBLKDAT);
outb(0x00, SMBBLKDAT);
outb(0xff, SMBBLKDAT);
outb(0xff, SMBBLKDAT);
outb(0xff, SMBBLKDAT);
outb(0xff, SMBBLKDAT);
}
//for (i=0; i < len; i++)
// outb(data[i],SMBBLKDAT);
outb(dev, SMBXMITADD);
outb(0, SMBHSTCMD);
outb(len, SMBHSTDAT0);
outb(0x74, SMBHSTCTL);
SMBUS_DELAY();
smbus_wait_until_ready();
smbus_reset();
return 0;
}
static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
{
@ -219,13 +163,6 @@ static void enable_smbus(void)
/* Make it work for I/O ... */
pci_write_config16(dev, 0x04, 0x0003);
/*
coreboot hangs at this two lines after os reboot(this even happen after I change os
reboot to cold reboot, this also interfere S3 wakeup) */
/* Setup clock chips */
//set_ics_data(0xd2, 0, 14);
//set_ics_data(0xd4, 0, 9);
smbus_reset();
/* clear host data port */
outb(0x00, SMBHSTDAT0);