From 17bb225be7dd031b9803f33dec88e9d53e3a582f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 19 Apr 2017 19:55:54 +0300 Subject: [PATCH] AMD MTRR: Add common add_uma_resource_below_tolm() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9eee88dc619ac5d9c77153db522a6ead65f6c9b1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/19376 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Marshall Dawson Reviewed-by: Paul Menzel --- src/cpu/amd/mtrr/amd_mtrr.c | 18 ++++++++++++++++++ src/include/cpu/amd/mtrr.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index a0a51943ab..9d9d7b7c19 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -76,6 +77,23 @@ static void setup_ap_ramtop(void) wrmsr(TOP_MEM2, msr); } +void add_uma_resource_below_tolm(struct device *nb, int idx) +{ + uint32_t topmem = bsp_topmem(); + uint32_t top_of_cacheable = get_top_of_ram(); + + if (top_of_cacheable == topmem) + return; + + uint32_t uma_base = top_of_cacheable; + uint32_t uma_size = topmem - top_of_cacheable; + + printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", + __func__, uma_size, uma_base); + + uma_resource(nb, idx, uma_base / KiB, uma_size / KiB); +} + void amd_setup_mtrrs(void) { unsigned long address_bits; diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index b65c23b83a..b31648d0af 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -41,6 +41,8 @@ #include void amd_setup_mtrrs(void); +struct device; +void add_uma_resource_below_tolm(struct device *nb, int idx); static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index) {