sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methods

Lynx Point PCH ACPI reference code version 1.9.1 has two additional
magic steps, which were already present in Broadwell. Add them.

Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-06-14 12:58:24 +02:00
parent c1328a6dba
commit 17c89018a5
1 changed files with 20 additions and 0 deletions

View File

@ -16,6 +16,14 @@ Device (XHCI)
Offset (0x10),
, 16,
XMEM, 16, // MEM_BASE
Offset (0x40),
, 11,
SWAI, 1,
, 20,
Offset (0x44),
, 12,
SAIP, 2,
, 18,
Offset (0x74),
D0D3, 2,
, 6,
@ -234,6 +242,12 @@ Device (XHCI)
CLK2 = 1
#endif
// Clear PCI CFG offset 0x40[11]
^SWAI = 0
// Clear PCI CFG offset 0x44[13:12]
^SAIP = 0
Return ()
}
@ -290,6 +304,12 @@ Device (XHCI)
CLK2 = 0
#endif
// Set PCI CFG offset 0x40[11]
^SWAI = 1
// Set PCI CFG offset 0x44[13:12]
^SAIP = 1
// Put device in D3
^D0D3 = 3