sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methods
Lynx Point PCH ACPI reference code version 1.9.1 has two additional magic steps, which were already present in Broadwell. Add them. Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -16,6 +16,14 @@ Device (XHCI)
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Offset (0x10),
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, 16,
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XMEM, 16, // MEM_BASE
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Offset (0x40),
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, 11,
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SWAI, 1,
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, 20,
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Offset (0x44),
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, 12,
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SAIP, 2,
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, 18,
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Offset (0x74),
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D0D3, 2,
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, 6,
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@ -234,6 +242,12 @@ Device (XHCI)
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CLK2 = 1
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#endif
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// Clear PCI CFG offset 0x40[11]
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^SWAI = 0
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// Clear PCI CFG offset 0x44[13:12]
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^SAIP = 0
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Return ()
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}
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@ -290,6 +304,12 @@ Device (XHCI)
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CLK2 = 0
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#endif
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// Set PCI CFG offset 0x40[11]
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^SWAI = 1
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// Set PCI CFG offset 0x44[13:12]
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^SAIP = 1
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// Put device in D3
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^D0D3 = 3
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