GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86 

Update header files for FSP for Meteor Lake platform to version
3323.86, previous version being 3323.84.

FSPM:
1. Added new UPDs
    - AcLoadline
    - DcLoadline
    - LowerBasicMemTestSize
2. Address offset changes

BUG=b:301441204
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Subrata Banik 2023-09-22 12:26:11 +05:30
parent 1d466f2a75
commit 17d619c25a
1 changed files with 74 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

120
src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
View File

@ -1426,7 +1426,25 @@ typedef struct {
/** Offset 0x0618 - Reserved /** Offset 0x0618 - Reserved
**/ **/
UINT8 Reserved33[126]; UINT8 Reserved33[12];
/** Offset 0x0624 - AcLoadline
AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT16 AcLoadline[6];
/** Offset 0x0630 - DcLoadline
DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55
mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for
GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT16 DcLoadline[6];
/** Offset 0x063C - Reserved
**/
UINT8 Reserved34[90];
/** Offset 0x0696 - Thermal Design Current enable/disable /** Offset 0x0696 - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA, Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@ -1443,7 +1461,7 @@ typedef struct {
/** Offset 0x06B4 - Reserved /** Offset 0x06B4 - Reserved
**/ **/
UINT8 Reserved34[166]; UINT8 Reserved35[166];
/** Offset 0x075A - VR Fast Vmode ICC Limit support /** Offset 0x075A - VR Fast Vmode ICC Limit support
Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@ -1469,7 +1487,7 @@ typedef struct {
/** Offset 0x0772 - Reserved /** Offset 0x0772 - Reserved
**/ **/
UINT8 Reserved35[146]; UINT8 Reserved36[146];
/** Offset 0x0804 - BiosGuard /** Offset 0x0804 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@ -1491,7 +1509,7 @@ typedef struct {
/** Offset 0x0807 - Reserved /** Offset 0x0807 - Reserved
**/ **/
UINT8 Reserved36; UINT8 Reserved37;
/** Offset 0x0808 - PrmrrSize /** Offset 0x0808 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@ -1505,7 +1523,7 @@ typedef struct {
/** Offset 0x0810 - Reserved /** Offset 0x0810 - Reserved
**/ **/
UINT8 Reserved37[8]; UINT8 Reserved38[8];
/** Offset 0x0818 - TxtDprMemoryBase /** Offset 0x0818 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
@ -1560,7 +1578,7 @@ typedef struct {
/** Offset 0x0849 - Reserved /** Offset 0x0849 - Reserved
**/ **/
UINT8 Reserved38[32]; UINT8 Reserved39[32];
/** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value. Enable PCH PCIe Gen 3 Set CTLE Value.
@ -1747,7 +1765,7 @@ typedef struct {
/** Offset 0x0A85 - Reserved /** Offset 0x0A85 - Reserved
**/ **/
UINT8 Reserved39; UINT8 Reserved40;
/** Offset 0x0A86 - SMBUS Base Address /** Offset 0x0A86 - SMBUS Base Address
SMBUS Base Address (IO space). SMBUS Base Address (IO space).
@ -1767,7 +1785,7 @@ typedef struct {
/** Offset 0x0A99 - Reserved /** Offset 0x0A99 - Reserved
**/ **/
UINT8 Reserved40[16]; UINT8 Reserved41[16];
/** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc Number of ClkReq signal assigned to ClkSrc
@ -1776,7 +1794,7 @@ typedef struct {
/** Offset 0x0AB9 - Reserved /** Offset 0x0AB9 - Reserved
**/ **/
UINT8 Reserved41[55]; UINT8 Reserved42[55];
/** Offset 0x0AF0 - Enable PCH PCIE RP Mask /** Offset 0x0AF0 - Enable PCH PCIE RP Mask
Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port,
@ -1828,7 +1846,7 @@ typedef struct {
/** Offset 0x0AFE - Reserved /** Offset 0x0AFE - Reserved
**/ **/
UINT8 Reserved42[2]; UINT8 Reserved43[2];
/** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number) /** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
@ -1848,7 +1866,7 @@ typedef struct {
/** Offset 0x0B11 - Reserved /** Offset 0x0B11 - Reserved
**/ **/
UINT8 Reserved43[3]; UINT8 Reserved44[3];
/** Offset 0x0B14 - DMIC<N> Data Pin Muxing /** Offset 0x0B14 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@ -1873,7 +1891,7 @@ typedef struct {
/** Offset 0x0B27 - Reserved /** Offset 0x0B27 - Reserved
**/ **/
UINT8 Reserved44; UINT8 Reserved45;
/** Offset 0x0B28 - iDisp-Link T-mode /** Offset 0x0B28 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
@ -1889,7 +1907,7 @@ typedef struct {
/** Offset 0x0B2A - Reserved /** Offset 0x0B2A - Reserved
**/ **/
UINT8 Reserved45[6]; UINT8 Reserved46[6];
/** Offset 0x0B30 - CNVi DDR RFI Mitigation /** Offset 0x0B30 - CNVi DDR RFI Mitigation
Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
@ -1899,7 +1917,7 @@ typedef struct {
/** Offset 0x0B31 - Reserved /** Offset 0x0B31 - Reserved
**/ **/
UINT8 Reserved46[11]; UINT8 Reserved47[11];
/** Offset 0x0B3C - Debug Interfaces /** Offset 0x0B3C - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
@ -1921,7 +1939,7 @@ typedef struct {
/** Offset 0x0B3F - Reserved /** Offset 0x0B3F - Reserved
**/ **/
UINT8 Reserved47; UINT8 Reserved48;
/** Offset 0x0B40 - Serial Io Uart Debug BaudRate /** Offset 0x0B40 - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@ -1949,7 +1967,7 @@ typedef struct {
/** Offset 0x0B47 - Reserved /** Offset 0x0B47 - Reserved
**/ **/
UINT8 Reserved48; UINT8 Reserved49;
/** Offset 0x0B48 - Serial Io Uart Debug Mmio Base /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
@ -1965,7 +1983,7 @@ typedef struct {
/** Offset 0x0B4D - Reserved /** Offset 0x0B4D - Reserved
**/ **/
UINT8 Reserved49; UINT8 Reserved50;
/** Offset 0x0B4E - Ring PLL voltage offset /** Offset 0x0B4E - Ring PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
@ -1979,7 +1997,7 @@ typedef struct {
/** Offset 0x0B50 - Reserved /** Offset 0x0B50 - Reserved
**/ **/
UINT8 Reserved50; UINT8 Reserved51;
/** Offset 0x0B51 - Memory Controller PLL voltage offset /** Offset 0x0B51 - Memory Controller PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
@ -2097,7 +2115,7 @@ typedef struct {
/** Offset 0x0B64 - Reserved /** Offset 0x0B64 - Reserved
**/ **/
UINT8 Reserved51; UINT8 Reserved52;
/** Offset 0x0B65 - Write Timing Centering 1D /** Offset 0x0B65 - Write Timing Centering 1D
Enables/Disable Write Timing Centering 1D Enables/Disable Write Timing Centering 1D
@ -2125,7 +2143,7 @@ typedef struct {
/** Offset 0x0B69 - Reserved /** Offset 0x0B69 - Reserved
**/ **/
UINT8 Reserved52[10]; UINT8 Reserved53[10];
/** Offset 0x0B73 - Read Equalization Training /** Offset 0x0B73 - Read Equalization Training
Enables/Disable Read Equalization Training Enables/Disable Read Equalization Training
@ -2135,7 +2153,7 @@ typedef struct {
/** Offset 0x0B74 - Reserved /** Offset 0x0B74 - Reserved
**/ **/
UINT8 Reserved53[2]; UINT8 Reserved54[2];
/** Offset 0x0B76 - Write Timing Centering 2D /** Offset 0x0B76 - Write Timing Centering 2D
Enables/Disable Write Timing Centering 2D Enables/Disable Write Timing Centering 2D
@ -2163,7 +2181,7 @@ typedef struct {
/** Offset 0x0B7A - Reserved /** Offset 0x0B7A - Reserved
**/ **/
UINT8 Reserved54; UINT8 Reserved55;
/** Offset 0x0B7B - Command Voltage Centering /** Offset 0x0B7B - Command Voltage Centering
Enables/Disable Command Voltage Centering Enables/Disable Command Voltage Centering
@ -2191,7 +2209,7 @@ typedef struct {
/** Offset 0x0B7F - Reserved /** Offset 0x0B7F - Reserved
**/ **/
UINT8 Reserved55; UINT8 Reserved56;
/** Offset 0x0B80 - DIMM SPD Alias Test /** Offset 0x0B80 - DIMM SPD Alias Test
Enables/Disable DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test
@ -2243,7 +2261,7 @@ typedef struct {
/** Offset 0x0B88 - Reserved /** Offset 0x0B88 - Reserved
**/ **/
UINT8 Reserved56[2]; UINT8 Reserved57[2];
/** Offset 0x0B8A - DIMM CA ODT Training /** Offset 0x0B8A - DIMM CA ODT Training
Enable/Disable DIMM CA ODT Training Enable/Disable DIMM CA ODT Training
@ -2253,7 +2271,7 @@ typedef struct {
/** Offset 0x0B8B - Reserved /** Offset 0x0B8B - Reserved
**/ **/
UINT8 Reserved57[3]; UINT8 Reserved58[3];
/** Offset 0x0B8E - Read Vref Decap Training /** Offset 0x0B8E - Read Vref Decap Training
Enable/Disable Read Vref Decap Training Enable/Disable Read Vref Decap Training
@ -2275,7 +2293,7 @@ typedef struct {
/** Offset 0x0B91 - Reserved /** Offset 0x0B91 - Reserved
**/ **/
UINT8 Reserved58[4]; UINT8 Reserved59[4];
/** Offset 0x0B95 - Duty Cycle Correction Training /** Offset 0x0B95 - Duty Cycle Correction Training
Enable/Disable Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training
@ -2285,7 +2303,7 @@ typedef struct {
/** Offset 0x0B96 - Reserved /** Offset 0x0B96 - Reserved
**/ **/
UINT8 Reserved59[17]; UINT8 Reserved60[17];
/** Offset 0x0BA7 - ECC Support /** Offset 0x0BA7 - ECC Support
Enables/Disable ECC Support Enables/Disable ECC Support
@ -2319,7 +2337,7 @@ typedef struct {
/** Offset 0x0BB3 - Reserved /** Offset 0x0BB3 - Reserved
**/ **/
UINT8 Reserved60; UINT8 Reserved61;
/** Offset 0x0BB4 - IbeccProtectedRegionBases /** Offset 0x0BB4 - IbeccProtectedRegionBases
IBECC Protected Region Bases per IBECC instance IBECC Protected Region Bases per IBECC instance
@ -2411,7 +2429,7 @@ typedef struct {
/** Offset 0x0BF0 - Reserved /** Offset 0x0BF0 - Reserved
**/ **/
UINT8 Reserved61[4]; UINT8 Reserved62[4];
/** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
@ -2670,7 +2688,7 @@ typedef struct {
/** Offset 0x0C2B - Reserved /** Offset 0x0C2B - Reserved
**/ **/
UINT8 Reserved62[2]; UINT8 Reserved63[2];
/** Offset 0x0C2D - Rapl Power Floor Ch0 /** Offset 0x0C2D - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def) Power budget ,range[255;0],(0= 5.3W Def)
@ -2721,7 +2739,7 @@ typedef struct {
/** Offset 0x0C35 - Reserved /** Offset 0x0C35 - Reserved
**/ **/
UINT8 Reserved63; UINT8 Reserved64;
/** Offset 0x0C36 - Power Down Mode /** Offset 0x0C36 - Power Down Mode
This option controls command bus tristating during idle periods This option controls command bus tristating during idle periods
@ -2758,7 +2776,7 @@ typedef struct {
/** Offset 0x0C3B - Reserved /** Offset 0x0C3B - Reserved
**/ **/
UINT8 Reserved64[8]; UINT8 Reserved65[8];
/** Offset 0x0C43 - Ask MRC to clear memory content /** Offset 0x0C43 - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
@ -2773,7 +2791,7 @@ typedef struct {
/** Offset 0x0C45 - Reserved /** Offset 0x0C45 - Reserved
**/ **/
UINT8 Reserved65; UINT8 Reserved66;
/** Offset 0x0C46 - Post Code Output Port /** Offset 0x0C46 - Post Code Output Port
This option configures Post Code Output Port This option configures Post Code Output Port
@ -2793,7 +2811,7 @@ typedef struct {
/** Offset 0x0C4A - Reserved /** Offset 0x0C4A - Reserved
**/ **/
UINT8 Reserved66[2]; UINT8 Reserved67[2];
/** Offset 0x0C4C - BCLK RFI Frequency /** Offset 0x0C4C - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@ -2836,7 +2854,7 @@ typedef struct {
/** Offset 0x0C62 - Reserved /** Offset 0x0C62 - Reserved
**/ **/
UINT8 Reserved67[11]; UINT8 Reserved68[11];
/** Offset 0x0C6D - RH pTRR LFSR1 Mask /** Offset 0x0C6D - RH pTRR LFSR1 Mask
Row Hammer pTRR LFSR1 Mask, 1/2^(value) Row Hammer pTRR LFSR1 Mask, 1/2^(value)
@ -2845,7 +2863,7 @@ typedef struct {
/** Offset 0x0C6E - Reserved /** Offset 0x0C6E - Reserved
**/ **/
UINT8 Reserved68; UINT8 Reserved69;
/** Offset 0x0C6F - Command Pins Mapping /** Offset 0x0C6F - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@ -2861,7 +2879,17 @@ typedef struct {
/** Offset 0x0C71 - Reserved /** Offset 0x0C71 - Reserved
**/ **/
UINT8 Reserved69[24]; UINT8 Reserved70[3];
/** Offset 0x0C74 - LowerBasicMemTestSize
Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 LowerBasicMemTestSize;
/** Offset 0x0C75 - Reserved
**/
UINT8 Reserved71[20];
/** Offset 0x0C89 - Skip external display device scanning /** Offset 0x0C89 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external Enable: Do not scan for external display device, Disable (Default): Scan external
@ -2897,7 +2925,7 @@ typedef struct {
/** Offset 0x0C8E - Reserved /** Offset 0x0C8E - Reserved
**/ **/
UINT8 Reserved70[2]; UINT8 Reserved72[2];
/** Offset 0x0C90 - PMR Size /** Offset 0x0C90 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@ -2911,7 +2939,7 @@ typedef struct {
/** Offset 0x0C95 - Reserved /** Offset 0x0C95 - Reserved
**/ **/
UINT8 Reserved71[143]; UINT8 Reserved73[143];
/** Offset 0x0D24 - TotalFlashSize /** Offset 0x0D24 - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@ -2927,7 +2955,7 @@ typedef struct {
/** Offset 0x0D28 - Reserved /** Offset 0x0D28 - Reserved
**/ **/
UINT8 Reserved72[28]; UINT8 Reserved74[28];
/** Offset 0x0D44 - Smbus dynamic power gating /** Offset 0x0D44 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating. Disable or Enable Smbus dynamic power gating.
@ -2943,7 +2971,7 @@ typedef struct {
/** Offset 0x0D46 - Reserved /** Offset 0x0D46 - Reserved
**/ **/
UINT8 Reserved73[2]; UINT8 Reserved75[2];
/** Offset 0x0D48 - SMBUS SPD Write Disable /** Offset 0x0D48 - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
@ -2954,7 +2982,7 @@ typedef struct {
/** Offset 0x0D49 - Reserved /** Offset 0x0D49 - Reserved
**/ **/
UINT8 Reserved74[34]; UINT8 Reserved76[34];
/** Offset 0x0D6B - HECI Timeouts /** Offset 0x0D6B - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI 0: Disable, 1: Enable (Default) timeout check for HECI
@ -3007,7 +3035,7 @@ typedef struct {
/** Offset 0x0D73 - Reserved /** Offset 0x0D73 - Reserved
**/ **/
UINT8 Reserved75[100]; UINT8 Reserved77[100];
/** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@ -3030,7 +3058,7 @@ typedef struct {
/** Offset 0x0DDA - Reserved /** Offset 0x0DDA - Reserved
**/ **/
UINT8 Reserved76[2]; UINT8 Reserved78[2];
/** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM
Select RX pin muxing for SerialIo UART used for debug Select RX pin muxing for SerialIo UART used for debug
@ -3056,7 +3084,7 @@ typedef struct {
/** Offset 0x0DEC - Reserved /** Offset 0x0DEC - Reserved
**/ **/
UINT8 Reserved77[164]; UINT8 Reserved79[164];
/** Offset 0x0E90 - TME Exclude Base Address /** Offset 0x0E90 - TME Exclude Base Address
TME Exclude Base Address. TME Exclude Base Address.
@ -3076,7 +3104,7 @@ typedef struct {
/** Offset 0x0EA1 - Reserved /** Offset 0x0EA1 - Reserved
**/ **/
UINT8 Reserved78[7]; UINT8 Reserved80[7];
} FSP_M_CONFIG; } FSP_M_CONFIG;
/** Fsp M UPD Configuration /** Fsp M UPD Configuration