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mb/google/brya/var/agah: Optimize dGPU GCOFF entry 

After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:

 - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
 - Remove delay after ramping down FBVDD

This patch implements these minor changes.

BUG=b:240199017
TEST=verified by EE

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak 2022-07-27 10:05:29 -06:00 committed by Paul Fagerburg
parent 1523742d4c
commit 17d71937a1
2 changed files with 1 additions and 4 deletions
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2
src/mainboard/google/brya/acpi/power.asl
View File

@ -174,7 +174,6 @@ Method (PGOF, 0, Serialized)
/* Assert PERST# */
\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
Sleep (5)
/* All rails are about to go down */
\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
@ -183,7 +182,6 @@ Method (PGOF, 0, Serialized)
/* Ramp down FBVDD (active-low) and let rail discharge to <10% */
\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
GPPL (GPIO_FBVDD_PG, 0, 20)
Sleep (40)
/* Ramp down PEXVDD and let rail discharge to <10% */
\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)

3
src/mainboard/google/brya/variants/agah/variant.c
View File

@ -56,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = {
/* In GCOFF entry order (i.e., power-off order) */
static const struct power_rail_sequence gpu_off_seq[] = {
{ "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 40,},
{ "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 0,},
{ "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 10,},
{ "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,},
{ "NV3_3", NV33_PWR_EN, false, NV33_PG, 4,},
@ -89,7 +89,6 @@ static void dgpu_power_sequence_off(void)
{
/* Assert reset and clear power-good */
gpio_output(GPU_PERST_L, 0);
mdelay(5);
/* Inform the GPU that the power is no longer good. */
gpio_output(GPU_ALLRAILS_PG, 0);