mainboard/google/kahlee: Update Grunt for 16MB ROM chip

- Update Grunt to 16MB chip in Kconfig.
- Move chromeos.fmd into variant directory & update Kconfig with the new
location.
- Add Grunt specific chromeos.fmd file.

BUG=b:69691210
TEST=Build grunt; Build & Boot Kahlee

Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Martin Roth 2017-11-22 20:30:17 -07:00
parent 320b41b148
commit 17e7a1e0e0
3 changed files with 51 additions and 1 deletions

View File

@ -16,7 +16,8 @@
config BOARD_GOOGLE_BASEBOARD_KAHLEE
bool
select SOC_AMD_STONEYRIDGE_FT4
select BOARD_ROMSIZE_KB_8192
select BOARD_ROMSIZE_KB_16384 if BOARD_GOOGLE_GRUNT
select BOARD_ROMSIZE_KB_8192 if BOARD_GOOGLE_KAHLEE
select DRIVERS_PS2_KEYBOARD
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
@ -53,6 +54,15 @@ config MAINBOARD_FAMILY
string
default "Google_Kahlee"
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/${CONFIG_VARIANT_DIR}/chromeos.fmd" if CHROMEOS
default ""
help
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
When an fmd is specified, it overrides the default format.
config MAX_CPUS
int
default 4

View File

@ -0,0 +1,40 @@
FLASH@0xFF000000 0x1000000 {
SI_BIOS@0x0 0x1000000 {
RW_SECTION_A@0x0 0x21E000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x20DFC0
RW_FWID_A@0x21DFC0 0x40
}
RW_SECTION_B@0x21E000 0x21E000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x20DFC0
RW_FWID_B@0x21DFC0 0x40
}
UNIFIED_MRC_CACHE@0x43C000 0x21000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
RW_VAR_MRC_CACHE@0x20000 0x1000
}
RW_ELOG@0x45D000 0x4000
RW_SHARED@0x461000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD@0x465000 0x2000
RW_UNUSED@0x467000 0x599000
RW_LEGACY@0xA00000 0x200000
WP_RO@0xC00000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0x17B000
RO_SECTION@0x17F000 0x281000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0x70000
COREBOOT(CBFS)@0x71000 0x210000
}
}
}
}