soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement

Expose a config option that allows enabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port.

This UPD is enabled by default in FSP but interferes with achieving
deeper S0ix substates so in order to prevent it from needing to be
explicitly disabled for every root port this change makes disabling it
the default and allows it to be enabled if needed.

BUG=b:160996445
TEST=boot on volteer with PTM disabled by default for all root ports
and ensure S0i3.2 substate can be achieved.

Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46856
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/chip.h

@@ -242,6 +242,9 @@ struct soc_intel_tigerlake_config {
 	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
 	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 
+	/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
+	uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
+
 	/* PCIe RP L1 substate */
 	enum L1_substates_control {
 		L1_SS_FSP_DEFAULT,

src/soc/intel/tigerlake/fsp_params.c

@@ -187,6 +187,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PcieRpAdvancedErrorReporting[i] =
 			config->PcieRpAdvancedErrorReporting[i];
 		params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+		params->PciePtm[i] = config->PciePtm[i];
 	}
 
 	/* Enable ClkReqDetect for enabled port */